mirror of https://github.com/parazyd/arm-sdk.git
142 lines
4.9 KiB
Diff
142 lines
4.9 KiB
Diff
From patchwork Thu Feb 8 18:30:35 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [PATCHv2,8/8] drm/omap: plane: update fifo size on ovl setup
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From: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
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X-Patchwork-Id: 10207743
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Message-Id: <20180208183035.8461-9-sebastian.reichel@collabora.co.uk>
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To: Sebastian Reichel <sre@kernel.org>,
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Tomi Valkeinen <tomi.valkeinen@ti.com>, Tony Lindgren <tony@atomide.com>
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Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
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Hans de Goede <hdegoede@redhat.com>, Rob Herring <robh+dt@kernel.org>,
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Mark Rutland <mark.rutland@arm.com>,
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dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
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linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org,
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kernel@collabora.com, Sebastian Reichel <sebastian.reichel@collabora.co.uk>
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Date: Thu, 8 Feb 2018 19:30:35 +0100
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This is a workaround for a hardware bug occuring on OMAP3
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with manually updated panels. Details about the HW bug are
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unknown to me, but without this fix the panel refresh does
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not work at all on Nokia N950. This is not the case for the
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OMAP4 based Droid 4, which works perfectly fine with default
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settings.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
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---
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drivers/gpu/drm/omapdrm/dss/dispc.c | 36 +++++++++++++++++++++++++++++++++++-
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1 file changed, 35 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
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index 4e8f68efd169..0904c3201914 100644
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--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
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+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
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@@ -157,6 +157,8 @@ struct dispc_features {
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bool has_gamma_table:1;
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bool has_gamma_i734_bug:1;
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+
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+ bool has_fifo_stallmode_bug:1;
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};
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#define DISPC_MAX_NR_FIFOS 5
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@@ -1489,6 +1491,18 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
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}
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}
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+static void dispc_ovl_set_manual_fifo_threshold(enum omap_plane_id plane)
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+{
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+ u32 fifo_low, fifo_high;
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+ bool use_fifo_merge = false;
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+ bool use_manual_update = true;
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+
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+ dispc_ovl_compute_fifo_thresholds(plane, &fifo_low, &fifo_high,
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+ use_fifo_merge, use_manual_update);
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+
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+ dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
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+}
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+
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static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable)
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{
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int bit;
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@@ -2651,8 +2665,21 @@ static int dispc_ovl_setup(enum omap_plane_id plane,
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oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
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oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
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oi->rotation_type, replication, vm, mem_to_mem);
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+ if (r)
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+ return r;
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- return r;
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+ /*
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+ * OMAP3 chips have non-working FIFO thresholds for manually updated
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+ * displays. The issue is not fully understood, but this workaround
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+ * fixes the issue. OMAP4 is known to work with default thresholds.
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+ */
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+ if (mgr_fld_read(channel, DISPC_MGR_FLD_STALLMODE) &&
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+ dispc.feat->has_fifo_stallmode_bug) {
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+ DSSDBG("Enable OMAP3 FIFO stallmode bug workaround!\n");
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+ dispc_ovl_set_manual_fifo_threshold(plane);
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+ }
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+
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+ return 0;
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}
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int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
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@@ -4067,6 +4094,7 @@ static const struct dispc_features omap24xx_dispc_feats = {
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.no_framedone_tv = true,
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.set_max_preload = false,
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.last_pixel_inc_missing = true,
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+ .has_fifo_stallmode_bug = true,
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};
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static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
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@@ -4101,6 +4129,7 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
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.no_framedone_tv = true,
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.set_max_preload = false,
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.last_pixel_inc_missing = true,
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+ .has_fifo_stallmode_bug = true,
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};
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static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
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@@ -4135,6 +4164,7 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
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.no_framedone_tv = true,
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.set_max_preload = false,
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.last_pixel_inc_missing = true,
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+ .has_fifo_stallmode_bug = true,
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};
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static const struct dispc_features omap36xx_dispc_feats = {
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@@ -4169,6 +4199,7 @@ static const struct dispc_features omap36xx_dispc_feats = {
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.no_framedone_tv = true,
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.set_max_preload = false,
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.last_pixel_inc_missing = true,
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+ .has_fifo_stallmode_bug = true,
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};
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static const struct dispc_features am43xx_dispc_feats = {
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@@ -4203,6 +4234,7 @@ static const struct dispc_features am43xx_dispc_feats = {
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.no_framedone_tv = true,
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.set_max_preload = false,
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.last_pixel_inc_missing = true,
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+ .has_fifo_stallmode_bug = false,
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};
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static const struct dispc_features omap44xx_dispc_feats = {
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@@ -4242,6 +4274,7 @@ static const struct dispc_features omap44xx_dispc_feats = {
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.reverse_ilace_field_order = true,
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.has_gamma_table = true,
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.has_gamma_i734_bug = true,
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+ .has_fifo_stallmode_bug = false,
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};
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static const struct dispc_features omap54xx_dispc_feats = {
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@@ -4282,6 +4315,7 @@ static const struct dispc_features omap54xx_dispc_feats = {
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.reverse_ilace_field_order = true,
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.has_gamma_table = true,
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.has_gamma_i734_bug = true,
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+ .has_fifo_stallmode_bug = false,
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};
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static irqreturn_t dispc_irq_handler(int irq, void *arg)
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