148 lines
5.1 KiB
Plaintext
148 lines
5.1 KiB
Plaintext
x86 optable reference
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---------------------
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(incomplete)
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P - modrm (reg mmx)
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PR - modrm (rm mmx, mod must be 11b)
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Q - modrm (rm mmx if mod=11b else mem)
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V - modrm (reg - xmm)
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VR - modrm (rm xmm, mod must be 11b)
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W - modrm (rm xmm if mod=11b else mem)
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MU - modrm (rm xmm if mod=11b else mem) lets us specify different sizes for reg and for mem.
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B - modrm (reg bounds)
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BM - modrm (rm bounds)
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K - modrm (reg opmask)
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KM - modrm (rm opmask if mod=11b else mem)
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KH - vex.vvvv (opmask)
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H - vex.vvvv xmm
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HR - vex.vvvv gpr
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L - xmm reg encoded in immediate byte
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XS - mem with base GPR and index XMM and a scale. (XSd, XSq)
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index will be xmm or ymm depending on vexl
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XSX - index will always be XMM
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XSY - index will always be YMM
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G - modrm (reg - gpr)
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S - modrm (reg - seg)
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VR - modrm (rm gpr, mod must be 11b)
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E - modrm (rm gpr if mod=11b else mem)
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M - modrm (mem), mod!=11b
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I - immediate
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J - relative immediate
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O - memory offset
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C - control reg
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D - debug reg
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opc <>
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/n - modrm reg field extends opcode
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/Mnn - disassembly mode extends opcode
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/Onn - operand mode extends opcode
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/mod=!11 - modrm mod field extends opcode
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<!--
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The most important elements of each instruction definition are the
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pfx (prefix), opc (opcode), and opr (operand) elements. Each is a
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CDATA element consisting of blank-separated words. Upper and lower
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case are equivalent.
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<pfx></pfx>
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pfx describes the set of valid prefixes that can precede the main
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opcode without turning it into a different instruction. These may
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be:
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aso accepts address size override
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oso accepts operand size override
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seg accepts a segment override
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rexw, rexr, rexx, rexb
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uses the indicated REX bit
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vexl accepts the vex.L prefix bit, in other words, the vexl
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bit can be used in the decoding of the avx instruction.
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<opr></opr>
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[T][s]
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Size Suffix
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===========
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x - If vex.L = 1 => m256/YMM
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vex.L = 0 => m128/XMM
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opc words may be actual byte values (two hex digits), or may be one of
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the following:
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/sse=66,f3,f2 - required prefix (always first, and always
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followed by 0f)
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/3dnow=00-ff - this is a 3DNow opcode (only in a definition of the
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form 0f 0f 3dnow=<byte>)
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/a=16,32,64 - has this address size
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/m=16,32,64,!64 - applicable only when the CPU is in this mode
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/o=16,32,64 - has this operand size
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/mod=11,!11 - has ModR/M with 11 or not-11 in the Mod field
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/reg=0-7 - has ModR/M with this value in the reg field
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/rm=0-7 - has ModR/M with this value in the R/M field (only with
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/mod=11)
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/x87=00-3f - X87 opcode with this value in the low 6 bits of the
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following "ModR/M" byte (only with /mod=11 and no other modifiers)
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opr words follow the Intel documentation somewhat, and specify the
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location and the size of the operand. The OperandDict table in
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ud_itab.py maps these words to named OP_ and SZ_ constants for the
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location and size respectively. These constants are defined in
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decode.h, q.v. for details.
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The mode element affects instruction semantics but not decoding:
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inv64 - invalid in 64-bit mode
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def64 - default operand size is 64 bits in 64-bit mode
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cpuid
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The cpuid element maybe applied to an instruction or a specific
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definition of the instruction. One ore more strings define the
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cpuid features that the instruction (or a definition belongs to)
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Values are: sse, sse2, sse3, sse4, sse4.1, sse4.2, avx
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AVX Instructions
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AVX instructions can be described in two ways. One, the explicit
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form, and the other that promotes an existing sse instruction
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definition to its avx form.
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If an instruction is defined to be in cpuid=avx, but is defined in
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the legacy form (using /sse= extensions), then the opcode generator
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will infer that as two definitions, one the see instruction and the
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other, an inferred avx instruction.
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In generating the sse definition from the above, the following
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transformations happen,
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- /vexw and /vexl extensions (if any) are removed
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- The operands H and L are removed. Operands specified on
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the right to removed operands are shifted to the left
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position.
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- The vexl prefix is removed.
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- "avx" is removed form the cpuid definition.
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In generating the avx definition from the above, the following
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transformations happen,
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- c4 is inserted in the 0th position of the opcode string
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- /sse extension is removed
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- A new /vex extension is constructed using /sse, 0f, 38 and
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3a opcodes (if any).
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- Operands V, W, H, and U are marked explicitly to have the
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size suffix "x"
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If the above transformations do not generate the required
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definitions, the instructions will need to be defined separately.
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--> |