From 53152dc58660d615a16771388ba0601cd91ccfc3 Mon Sep 17 00:00:00 2001
From: Marco Massarelli <marco.massarelli@gmail.com>
Date: Fri, 26 Jan 2024 18:36:47 +0000
Subject: [PATCH] Correct the minimum via size for JLCPCB

---
 ergogen/footprints/sk6812mini-e.js | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ergogen/footprints/sk6812mini-e.js b/ergogen/footprints/sk6812mini-e.js
index fb0a691..3169051 100644
--- a/ergogen/footprints/sk6812mini-e.js
+++ b/ergogen/footprints/sk6812mini-e.js
@@ -13,8 +13,8 @@ module.exports = {
     gnd_trace_width: 0.25, // Max 0.8 to avoid clearance errors
     pwr_trace_width: 0.25, // Max 0.8 to avoid clearance errors
     signal_trace_width: 0.15,
-    via_size: 0.8, // JLCPC min is 0.5 for 1-2 layer boards, KiCad defaults to 0.8
-    via_drill: 0.4, // JLCPC min is 0.3 for 1-2 layer boards, KiCad defaults to 0.4
+    via_size: 0.8, // JLCPCB min is 0.56 for 1-2 layer boards, KiCad defaults to 0.8
+    via_drill: 0.4, // JLCPCB min is 0.3 for 1-2 layer boards, KiCad defaults to 0.4
     side: 'B',
   },
   body: p => {