From faf4d96fb7db67009afff4ee50681e10343633d2 Mon Sep 17 00:00:00 2001
From: Marco Massarelli <marco.massarelli@gmail.com>
Date: Tue, 26 Sep 2023 16:55:46 -0400
Subject: [PATCH] Add initial support for KiBot and KiCad 7 CI/CD

---
 .github/workflows/build.yaml |  1 +
 .gitignore                   |  4 +-
 build.sh                     | 21 ++-------
 kibot/boards.kibot.yaml      | 87 ++++++++++++++++++++++++++++++++++++
 kibot/export_dsn.py          | 30 +++++++++++++
 5 files changed, 123 insertions(+), 20 deletions(-)
 create mode 100644 kibot/boards.kibot.yaml
 create mode 100755 kibot/export_dsn.py

diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml
index 6d16d05..a4d6073 100644
--- a/.github/workflows/build.yaml
+++ b/.github/workflows/build.yaml
@@ -4,6 +4,7 @@ on:
     paths:
       - 'ergogen/footprints/*.js'
       - 'ergogen/config.yaml'
+      - 'kibot/*.yaml'
       - '.github/workflows/*.yaml'
       - '.github/actions/*/action.yaml'
       - 'package.json'
diff --git a/.gitignore b/.gitignore
index cecd5ca..f1b11a1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -43,5 +43,5 @@ ergogen/output/source
 node_modules
 
 # gerbers
-ergogen/output/gerbers/*
-!ergogen/output/gerbers/*.zip
\ No newline at end of file
+ergogen/output/gerbers/*/*
+!ergogen/output/gerbers/*/*.zip
\ No newline at end of file
diff --git a/build.sh b/build.sh
index a810002..f18e59c 100755
--- a/build.sh
+++ b/build.sh
@@ -24,13 +24,7 @@ pcbdraw_style=set-black-hasl
 for plate in ${plates}
 do
     echo "\n\n>>>>>> Processing $plate <<<<<<\n\n"
-    echo "Export Gerbers"
-    mkdir -p ergogen/output/gerbers/${plate}
-    ${container_cmd} run ${container_args} yaqwsx/kikit:v1.1.2 kikit fab ${fab} ${flags} --no-drc ergogen/output/pcbs/${plate}.kicad_pcb ergogen/output/gerbers/${plate}
-    mv ergogen/output/gerbers/${plate}/gerbers.zip ergogen/output/gerbers/${plate}.zip
-    echo "Generate PCB images"
-    mkdir -p ergogen/output/images
-    ${container_cmd} run ${container_args} yaqwsx/kikit:v1.1.2 pcbdraw plot --style ${pcbdraw_style} ergogen/output/pcbs/${plate}.kicad_pcb ergogen/output/images/${plate}.svg
+    ${container_cmd} run ${container_args} ghcr.io/inti-cmnb/kicad7_auto:1.6.2 kibot -b ergogen/output/pcbs/${plate}.kicad_pcb -c kibot/boards.kibot.yaml
 done
 
 for board in ${boards}
@@ -39,7 +33,7 @@ do
     ${container_cmd} run ${container_args} soundmonster/kicad-automation-scripts:latest /bin/sh -c "mkdir -p $HOME/.config/kicad; cp /root/.config/kicad/* $HOME/.config/kicad"
     if [ -e ergogen/output/pcbs/${board}.kicad_pcb ]; then
         echo Export DSN 
-        ${container_cmd} run ${container_args} soundmonster/kicad-automation-scripts:latest /usr/lib/python2.7/dist-packages/kicad-automation/pcbnew_automation/export_dsn.py ergogen/output/pcbs/${board}.kicad_pcb ergogen/output/pcbs/${board}.dsn    
+        ${container_cmd} run ${container_args} ghcr.io/inti-cmnb/kicad7_auto:1.6.2 kibot/export_dsn.py -b ergogen/output/pcbs/${board}.kicad_pcb -o ergogen/output/pcbs/${board}.dsn    
     fi
     if [ -e ergogen/output/pcbs/${board}.dsn ]; then
         echo Autoroute PCB
@@ -50,15 +44,6 @@ do
         ${container_cmd} run ${container_args} soundmonster/kicad-automation-scripts:latest /usr/lib/python2.7/dist-packages/kicad-automation/pcbnew_automation/import_ses.py ergogen/output/pcbs/${board}.kicad_pcb ergogen/output/pcbs/${board}.ses --output-file ergogen/output/pcbs/${board}_routed.kicad_pcb
     fi
     if [ -e ergogen/output/pcbs/${board}_routed.kicad_pcb ]; then
-        echo "DRC check"
-        ${container_cmd} run ${container_args} soundmonster/kicad-automation-scripts:latest /usr/lib/python2.7/dist-packages/kicad-automation/pcbnew_automation/run_drc.py $GITHUB_WORKSPACE/ergogen/output/pcbs/${board}_routed.kicad_pcb $GITHUB_WORKSPACE/ergogen/output/pcbs/${board}_drc/
-        echo "Export Gerbers"
-        mkdir -p ergogen/output/gerbers/${board}
-        ${container_cmd} run ${container_args} yaqwsx/kikit:v0.7 kikit fab ${fab} ${flags} ergogen/output/pcbs/${board}_routed.kicad_pcb ergogen/output/gerbers/${board}
-        mv ergogen/output/gerbers/${board}/gerbers.zip ergogen/output/gerbers/${board}.zip
-        echo "Generate PCB images"
-        mkdir -p ergogen/output/images
-        ${container_cmd} run ${container_args} yaqwsx/kikit:v0.7 pcbdraw --style builtin:${pcbdraw_style}.json ergogen/output/pcbs/${board}_routed.kicad_pcb ergogen/output/images/${board}_front.png
-        ${container_cmd} run ${container_args} yaqwsx/kikit:v0.7 pcbdraw -b --style builtin:${pcbdraw_style}.json ergogen/output/pcbs/${board}_routed.kicad_pcb ergogen/output/images/${board}_back.png
+        ${container_cmd} run ${container_args} ghcr.io/inti-cmnb/kicad7_auto:1.6.2 kibot -b ergogen/output/pcbs/${board}_routed.kicad_pcb -c kibot/boards.kibot.yaml
     fi
 done
\ No newline at end of file
diff --git a/kibot/boards.kibot.yaml b/kibot/boards.kibot.yaml
new file mode 100644
index 0000000..d53cc53
--- /dev/null
+++ b/kibot/boards.kibot.yaml
@@ -0,0 +1,87 @@
+# Gerber and drill files for JLCPCB, without stencil, plus board images
+# URL: https://jlcpcb.com/help/article/16-How-to-generate-Gerber-and-Drill-files-in-KiCad-6
+
+kibot:
+  version: 1
+
+preflight:
+  run_erc: false
+  update_xml: false
+  run_drc: false
+  check_zone_fills: true
+  ignore_unconnected: false
+
+outputs:
+  - name: jlcpcb_gerbers
+    comment: Gerbers compatible with JLCPCB
+    type: gerber
+    dir: ergogen/output/gerbers/%f
+    options: &gerber_options
+      exclude_edge_layer: true
+      exclude_pads_from_silkscreen: true
+      plot_sheet_reference: false
+      plot_footprint_refs: true
+      plot_footprint_values: false
+      force_plot_invisible_refs_vals: false
+      tent_vias: true
+      use_protel_extensions: true
+      create_gerber_job_file: false
+      disable_aperture_macros: true
+      gerber_precision: 4.6
+      use_gerber_x2_attributes: false
+      use_gerber_net_attributes: false
+      line_width: 0.1
+      subtract_mask_from_silk: true
+    layers:
+      # Note: a more generic approach is to use 'copper' but then the filenames
+      # are slightly different.
+      - F.Cu
+      - B.Cu
+      - F.SilkS
+      - B.SilkS
+      - F.Mask
+      - B.Mask
+      - Edge.Cuts
+
+  - name: jlcpcb_drill
+    comment: Drill files compatible with JLCPCB
+    type: excellon
+    dir: ergogen/output/gerbers/%f
+    options:
+      mirror_y_axis: false
+      minimal_header: false
+      pth_and_npth_single_file: false
+      route_mode_for_oval_holes: false
+      map: gerber
+      use_aux_axis_as_origin: false
+      metric_units: true
+      zeros_format: 'DECIMAL_FORMAT'
+
+  - name: jlcpcb
+    comment: ZIP file for JLCPCB gerbers
+    type: compress
+    dir: ergogen/output/gerbers
+    options:
+      files:
+        - from_output: jlcpcb_gerbers
+          dest: /
+        - from_output: jlcpcb_drill
+          dest: /
+      output: '%f.%x'
+
+  - name: top_view
+    comment: "Top view of the PCB"
+    type: pcbdraw
+    dir: ergogen/output/images
+    options:
+      format: png
+      style: oshpark-afterdark
+      margin: 5
+
+  - name: bottom_view
+    comment: "Bottom view of the PCB"
+    type: pcbdraw
+    dir: ergogen/output/images
+    extends: top_view
+    options:
+      bottom: true
diff --git a/kibot/export_dsn.py b/kibot/export_dsn.py
new file mode 100755
index 0000000..7efb769
--- /dev/null
+++ b/kibot/export_dsn.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+import sys, getopt
+import pcbnew
+"""
+This program runs pcbnew and exports a Specctra DSN file. 
+"""
+
+def main(argv):
+  board_file = ''
+  output_file = ''
+  try:
+    opts, args = getopt.getopt(argv, "hb:o:",["board=","output="])
+  except getopt.GetoptError:
+    print ('export_dsn.py -b <board_file> -o <ouput_dsn_file>')
+    sys.exit(2)
+  for opt, arg in opts:
+    if opt == '-h': 
+      print ('export_dsn.py -b <board_file> -o <ouput_dsn_file>')
+      sys.exit()
+    elif opt in ("-b", "--board"):
+      board_file = arg
+    elif opt in ("-o", "--output"):
+      output_file = arg
+  print('Exporting Specctra DSN for ', board_file, ' at ', output_file)
+  board = pcbnew.LoadBoard(board_file)
+  pcbnew.ExportSpecctraDSN(board, output_file)
+
+if __name__ == "__main__":
+   main(sys.argv[1:])
\ No newline at end of file