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[Tests] Separated kicad2step, pcbnew and eeschema tests

This commit is contained in:
Salvador E. Tropea 2022-07-14 19:23:28 -03:00
parent 5a8391ca59
commit 061ed0488e
6 changed files with 39 additions and 0 deletions
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3
pytest.ini
View File

@ -3,3 +3,6 @@ python_files = tests/test_plot/test_*.py
markers =
webtest: mark a test as a webtest.
slow: mark test as slow.
kicad2step: uses kicad2step tool
eeschema: uses eeschema tool
pcbnew: uses pcbnew tool

8
tests/test_plot/test_misc.py
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@ -744,6 +744,7 @@ def check_makefile(ctx, mkfile, prj, dbg, txt):
@pytest.mark.slow
@pytest.mark.kicad2step
def test_makefile_1(test_dir):
prj = 'test_v5'
ctx = context.TestContext(test_dir, prj, 'makefile_1')
@ -755,6 +756,7 @@ def test_makefile_1(test_dir):
@pytest.mark.slow
@pytest.mark.kicad2step
def test_makefile_2(test_dir):
prj = 'test_v5'
ctx = context.TestContext(test_dir, prj, 'makefile_1')
@ -939,6 +941,7 @@ def test_cli_order(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_qr_lib_1(test_dir):
prj = 'qr_test/qr_test'
ctx = context.TestContext(test_dir, prj, 'qr_lib_1', POS_DIR)
@ -1001,6 +1004,7 @@ def test_report_simple_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_report_simple_2(test_dir):
prj = 'light_control'
ctx = context.TestContext(test_dir, prj, 'report_simple_2', POS_DIR)
@ -1160,6 +1164,7 @@ def test_annotate_pcb_tbrl_small_grid(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_gencad_1(test_dir):
prj = 'gencad'
ctx = context.TestContext(test_dir, prj, 'gencad_1')
@ -1177,6 +1182,7 @@ def test_gencad_1(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_quick_start_1(test_dir):
""" Very naive test to see if it doesn't crash """
prj = 'light_control'
@ -1217,6 +1223,7 @@ def test_quick_start_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_netlist_classic_1(test_dir):
prj = 'light_control'
dir_o = 'Export'
@ -1226,6 +1233,7 @@ def test_netlist_classic_1(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_netlist_ipc_1(test_dir):
prj = 'light_control'
dir_o = 'Export'

6
tests/test_plot/test_preflight.py
View File

@ -24,6 +24,7 @@ from kibot.misc import DRC_ERROR, ERC_ERROR, BOM_ERROR, CORRUPTED_PCB, CORRUPTED
@pytest.mark.slow
@pytest.mark.eeschema
def test_erc_1(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'erc', '')
@ -34,6 +35,7 @@ def test_erc_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_erc_fail_1(test_dir):
""" Using an SCH with ERC errors """
prj = 'fail-erc'
@ -53,6 +55,7 @@ def test_erc_fail_2(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_erc_warning_1(test_dir):
""" Using an SCH with ERC warnings """
prj = 'warning-project'
@ -65,6 +68,7 @@ def test_erc_warning_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_erc_warning_2(test_dir):
""" Using an SCH with ERC warnings as errors """
prj = 'warning-project'
@ -136,6 +140,7 @@ def test_drc_time_out(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_update_xml_1(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'update_xml', '')
@ -156,6 +161,7 @@ def test_update_xml_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_update_xml_fail(test_dir):
""" Using a dummy SCH """
prj = '3Rs'

9
tests/test_plot/test_print_pcb.py
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@ -18,6 +18,7 @@ PDF_FILE_C = 'PCB_Bot_def.pdf'
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_pcb_simple(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'print_pcb', PDF_DIR)
@ -28,6 +29,7 @@ def test_print_pcb_simple(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_pcb_svg_simple_1(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'print_pcb_svg')
@ -40,6 +42,7 @@ def test_print_pcb_svg_simple_1(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_pcb_svg_simple_2(test_dir):
""" Check the portrait version is OK """
prj = 'bom_portrait'
@ -53,6 +56,7 @@ def test_print_pcb_svg_simple_2(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_pcb_refill_1(test_dir):
prj = 'zone-refill'
ctx = context.TestContext(test_dir, prj, 'print_pcb_zone-refill')
@ -63,6 +67,7 @@ def test_print_pcb_refill_1(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_pcb_refill_2(test_dir):
""" Using KiCad 6 colors """
if context.ki5():
@ -76,6 +81,7 @@ def test_print_pcb_refill_2(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_variant_1(test_dir):
prj = 'kibom-variant_3_txt'
ctx = context.TestContext(test_dir, prj, 'print_pcb_variant_1')
@ -89,6 +95,7 @@ def test_print_variant_1(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_pcb_options(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'print_pcb_options', PDF_DIR)
@ -100,6 +107,7 @@ def test_print_pcb_options(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_print_wrong_paste(test_dir):
prj = 'wrong_paste'
ctx = context.TestContext(test_dir, prj, 'wrong_paste', PDF_DIR)
@ -111,6 +119,7 @@ def test_print_wrong_paste(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_pcb_print_simple_1(test_dir):
prj = 'light_control'
ctx = context.TestContext(test_dir, prj, 'pcb_print_2')

7
tests/test_plot/test_print_sch.py
View File

@ -27,6 +27,7 @@ cov = coverage.Coverage()
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_ok(test_dir):
prj = 'bom_no_xml' # bom has meta data, here we test no meta-data
ctx = context.TestContext(test_dir, prj, 'print_sch')
@ -37,6 +38,7 @@ def test_print_sch_ok(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_fail(test_dir):
prj = 'print_err'
ctx = context.TestContextSCH(test_dir, prj, 'print_sch')
@ -46,6 +48,7 @@ def test_print_sch_fail(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_svg_ok(test_dir):
prj = 'bom_no_xml' # bom has meta data, here we test no meta-data
ctx = context.TestContext(test_dir, prj, 'print_sch_svg')
@ -56,6 +59,7 @@ def test_print_sch_svg_ok(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_svg_fail(test_dir):
prj = 'print_err'
ctx = context.TestContext(test_dir, prj, 'print_sch_svg')
@ -103,6 +107,7 @@ def test_sch_variant_ni_2(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_variant_ni_1(test_dir):
""" Using a variant """
prj = 'test_v5_wks' # Is the most complete, contains every KiCad object I know
@ -116,6 +121,7 @@ def test_print_sch_variant_ni_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_svg_variant_ni_1(test_dir):
""" SVG using a variant """
prj = 'test_v5' # Is the most complete, contains every KiCad object I know
@ -129,6 +135,7 @@ def test_print_sch_svg_variant_ni_1(test_dir):
@pytest.mark.slow
@pytest.mark.eeschema
def test_print_sch_variant_ni_2(test_dir):
""" Using a filter """
prj = 'test_v5' # Is the most complete, contains every KiCad object I know

6
tests/test_plot/test_step.py
View File

@ -19,6 +19,7 @@ STEP_DIR = '3D'
@pytest.mark.slow
@pytest.mark.kicad2step
def test_step_1(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'step_simple', STEP_DIR)
@ -34,6 +35,7 @@ def test_step_1(test_dir):
@pytest.mark.slow
@pytest.mark.kicad2step
def test_step_2(test_dir):
prj = 'bom_fake_models'
yaml = 'step_simple_2'
@ -48,6 +50,7 @@ def test_step_2(test_dir):
@pytest.mark.slow
@pytest.mark.kicad2step
def test_step_3(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'step_simple_3', STEP_DIR)
@ -58,6 +61,7 @@ def test_step_3(test_dir):
@pytest.mark.slow
@pytest.mark.kicad2step
def test_step_gl_env(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'step_gl_env', STEP_DIR)
@ -73,6 +77,7 @@ def test_step_gl_env(test_dir):
@pytest.mark.slow
@pytest.mark.kicad2step
def test_step_variant_1(test_dir):
prj = 'kibom-variant_3'
ctx = context.TestContext(test_dir, prj, 'step_variant_1')
@ -85,6 +90,7 @@ def test_step_variant_1(test_dir):
@pytest.mark.slow
@pytest.mark.pcbnew
def test_render_3d_variant_1(test_dir):
# Text variables to ensure they are rendered.
# Traces