From 0d9256fb244d4f08c890be9b720308b90051920c Mon Sep 17 00:00:00 2001
From: "Salvador E. Tropea" <salvador@inti.gob.ar>
Date: Sun, 14 Jun 2020 15:12:56 -0300
Subject: [PATCH] The 'check_zone_fills' option is now independent of 'run_drc'

Implemented in a different way.
For all internal commands now we use Python bindings to fill the zones as
suggested by @arikrupnik in johnbeard/kiplot#11
For 'print_pcb' now we ask KiCad to do it before printing (needs v1.4.1)
---
 CHANGELOG.md                                  |   3 +
 Makefile                                      |  12 +-
 README.md                                     |   6 +-
 kiplot/kiplot.py                              |  20 +-
 tests/board_samples/zone-refill.kicad_pcb     | 339 +++++++++++++++++
 tests/board_samples/zone-refill.kicad_pcb.ok  | 339 +++++++++++++++++
 .../zone-refill.kicad_pcb.refill              | 352 ++++++++++++++++++
 tests/reference/PCB_Bot.pdf                   | Bin 0 -> 10692 bytes
 tests/reference/zone-refill-B_Cu.pdf          | Bin 0 -> 4886 bytes
 tests/test_plot/test_pdf.py                   |  10 +
 tests/test_plot/test_print_pcb.py             |  10 +
 tests/utils/context.py                        |   5 +-
 .../yaml_samples/pdf_zone-refill.kiplot.yaml  |  31 ++
 .../print_pcb_zone-refill.kiplot.yaml         |  17 +
 14 files changed, 1128 insertions(+), 16 deletions(-)
 create mode 100644 tests/board_samples/zone-refill.kicad_pcb
 create mode 100644 tests/board_samples/zone-refill.kicad_pcb.ok
 create mode 100644 tests/board_samples/zone-refill.kicad_pcb.refill
 create mode 100644 tests/reference/PCB_Bot.pdf
 create mode 100644 tests/reference/zone-refill-B_Cu.pdf
 create mode 100644 tests/yaml_samples/pdf_zone-refill.kiplot.yaml
 create mode 100644 tests/yaml_samples/print_pcb_zone-refill.kiplot.yaml

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 34f1d450..52c2169f 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -9,9 +9,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Added
 - Better debug information when a BoM fails to be generated.
 - Support for compressed YAML files.
+
 ### Changed
 - Allowed operations that doesn't involve a PCB now can run if the PCB file is
   missing or corrupted.
+- The 'check_zone_fills' option is now independent of 'run_drc'
+
 ### Fixed
 - Error codes that overlapped.
 
diff --git a/Makefile b/Makefile
index 6bee753c..e5939b2f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,10 +1,11 @@
 #!/usr/bin/make
 PY_COV=python3-coverage
+REFDIR=tests/reference/
+REFILL=tests/board_samples/zone-refill.kicad_pcb
 CWD := $(abspath $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
 USER_ID=$(shell id -u)
 GROUP_ID=$(shell id -g)
 
-
 deb:
 	fakeroot dpkg-buildpackage -uc -b
 
@@ -43,4 +44,11 @@ test_docker_local:
 deb_clean:
 	fakeroot debian/rules clean
 
-.PHONY: deb deb_clean lint test test_local
+gen_ref:
+	# Reference outputs, must be manually inspected if regenerated
+	cp -a $(REFILL).refill $(REFILL)
+	src/kiplot -c tests/yaml_samples/pdf_zone-refill.kiplot.yaml -b tests/board_samples/zone-refill.kicad_pcb -d $(REFDIR)
+	src/kiplot -c tests/yaml_samples/print_pcb_zone-refill.kiplot.yaml -b tests/board_samples/zone-refill.kicad_pcb -d $(REFDIR)
+	cp -a $(REFILL).ok $(REFILL)
+
+.PHONY: deb deb_clean lint test test_local gen_ref
diff --git a/README.md b/README.md
index 5920285b..90f68c6e 100644
--- a/README.md
+++ b/README.md
@@ -51,9 +51,9 @@ This section is used to specify tasks that will executed before generating any o
 - `run_erc` To run the ERC (Electrical Rules Check). To ensure the schematic is electrically correct. 
 - `run_drc` To run the DRC (Distance Rules Check). To ensure we have a valid PCB.
 - `update_xml` To update the XML version of the BoM (Bill of Materials). To ensure our generated BoM is up to date.
+- `check_zone_fills` Zones are filled before doing any operation involving PCB layers.
  
-The `run_drc` command has the following options:
-- `check_zone_fills` Every time we run the DRC the zones are filled again. This option saves the PCB to disk updating the zones.
+The `run_drc` command has the following option:
 - `ignore_unconnected` Ignores the unconnected nets. Useful if you didn't finish the routing.
 
 Here is an example of a *preflight* section:
@@ -169,7 +169,6 @@ outputs:
       plot_footprint_values: true
       force_plot_invisible_refs_vals: false
       tent_vias: true
-      check_zone_fills: true
       line_width: 0.15
 
       # gerber options
@@ -199,7 +198,6 @@ Most options are the same you'll find in the KiCad dialogs.
 - `plot_footprint_values` include the footprint values
 - `force_plot_invisible_refs_vals` include references and values even when they are marked as invisible
 - `tent_vias` cover the vias
-- `check_zone_fills` currently without effect
 
 Note that each layer is generated in a separated file.
 
diff --git a/kiplot/kiplot.py b/kiplot/kiplot.py
index 9298df76..4056884f 100644
--- a/kiplot/kiplot.py
+++ b/kiplot/kiplot.py
@@ -134,6 +134,8 @@ class Plotter(object):
     def _load_board(self, brd_file):
         try:
             board = pcbnew.LoadBoard(brd_file)
+            if self.cfg.check_zone_fills:
+                pcbnew.ZONE_FILLER(board).Fill(board.Zones())
         except OSError as e:
             logger.error('Error loading PCB file. Currupted?')
             logger.error(e)
@@ -165,6 +167,9 @@ class Plotter(object):
                     elif skip == 'run_erc':
                         self.cfg.run_erc = False
                         logger.debug('Skipping run_erc')
+                    elif skip == 'check_zone_fills':
+                        self.cfg.check_zone_fills = False
+                        logger.debug('Skipping run_erc')
                     else:
                         logger.error('Unknown action to skip: '+skip)
                         exit(misc.EXIT_BAD_ARGS)
@@ -179,8 +184,7 @@ class Plotter(object):
         if self.cfg.update_xml:
             self._update_xml(brd_file)
         if self.cfg.run_drc:
-            self._run_drc(brd_file, self.cfg.ignore_unconnected,
-                          self.cfg.check_zone_fills, filter_file)
+            self._run_drc(brd_file, self.cfg.ignore_unconnected, filter_file)
 
     def _run_erc(self, brd_file, filter_file):
         sch_file = check_eeschema_do(brd_file)
@@ -216,7 +220,7 @@ class Plotter(object):
             logger.error('Failed to update the BoM, error %d', ret)
             exit(misc.BOM_ERROR)
 
-    def _run_drc(self, brd_file, ignore_unconnected, check_zone_fills, filter_file):
+    def _run_drc(self, brd_file, ignore_unconnected, filter_file):
         check_script(misc.CMD_PCBNEW_RUN_DRC, misc.URL_PCBNEW_RUN_DRC, '1.4.0')
         cmd = [misc.CMD_PCBNEW_RUN_DRC, 'run_drc']
         if filter_file:
@@ -228,8 +232,6 @@ class Plotter(object):
             cmd.insert(1, '-r')
         if ignore_unconnected:
             cmd.insert(1, '-i')
-        if check_zone_fills:
-            cmd.insert(1, '-s')
         logger.info('- Running the DRC')
         logger.debug('Executing: '+str(cmd))
         ret = call(cmd)
@@ -602,7 +604,7 @@ class Plotter(object):
 
     def _do_pcb_print(self, board, output_dir, output, brd_file):
         check_script(misc.CMD_PCBNEW_PRINT_LAYERS,
-                     misc.URL_PCBNEW_PRINT_LAYERS, '1.3.1')
+                     misc.URL_PCBNEW_PRINT_LAYERS, '1.4.1')
         to = output.options.type_options
         # Verify the inner layers
         layer_cnt = board.GetCopperLayerCount()
@@ -615,8 +617,10 @@ class Plotter(object):
                             "Inner layer {} is not valid for this board"
                             .format(layer.layer))
         cmd = [misc.CMD_PCBNEW_PRINT_LAYERS, 'export',
-               '--output_name', to.output_name,
-               brd_file, output_dir]
+               '--output_name', to.output_name]
+        if self.cfg.check_zone_fills:
+            cmd.append('-f')
+        cmd.extend([brd_file, output_dir])
         if level_debug():
             cmd.insert(1, '-vv')
             cmd.insert(1, '-r')
diff --git a/tests/board_samples/zone-refill.kicad_pcb b/tests/board_samples/zone-refill.kicad_pcb
new file mode 100644
index 00000000..2cba7e7d
--- /dev/null
+++ b/tests/board_samples/zone-refill.kicad_pcb
@@ -0,0 +1,339 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2~bpo10+1)
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 10)
+    (zones 0)
+    (modules 4)
+    (nets 4)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 GND)
+  (net 2 "Net-(C1-Pad1)")
+  (net 3 "Net-(J1-Pad1)")
+
+  (net_class Default "Esta es la clase de red por defecto."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net "Net-(C1-Pad1)")
+    (add_net "Net-(J1-Pad1)")
+  )
+
+  (module Resistor_SMD:R_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC712)
+    (at 161.9375 74 180)
+    (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5EBAD9A3)
+    (attr smd)
+    (fp_text reference R1 (at 0 1.65) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value R (at 0 -1.65) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+    )
+    (fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 "Net-(J1-Pad1)"))
+    (pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 2 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC57B)
+    (at 167 77.54 180)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5EBAC9BE)
+    (fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02_Male (at -4 4.87) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad1)"))
+    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC6B7)
+    (at 157.82 74.85)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5EBAC114)
+    (fp_text reference J1 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02_Male (at -4.82 5.15) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 "Net-(J1-Pad1)"))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC54F)
+    (at 163 77.0625 270)
+    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5EBAE412)
+    (attr smd)
+    (fp_text reference C1 (at 0 1.65 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value C (at 0 -1.65 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+    )
+    (fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 1 GND))
+    (pad 1 smd roundrect (at -0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 2 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 170 80) (end 169 80) (layer Edge.Cuts) (width 0.05) (tstamp 5EBAC92C))
+  (gr_line (start 170 72) (end 170 80) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 155 72) (end 170 72) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 155 80) (end 155 72) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 169 80) (end 155 80) (layer Edge.Cuts) (width 0.05))
+
+  (segment (start 162.39 77.39) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 157.82 77.39) (end 162.39 77.39) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 163.46 77.54) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 167 77.54) (end 163.46 77.54) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 167 75) (end 164 75) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 164 75) (end 163 76) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 164 75) (end 163 74) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 159.7 74) (end 161 74) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 157.82 74.85) (end 158.92 74.85) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 158.92 74.85) (end 159.7 74) (width 0.25) (layer B.Cu) (net 3))
+
+  (zone (net 1) (net_name GND) (layer B.Cu) (tstamp 5EBAC970) (hatch edge 0.508)
+    (connect_pads (clearance 0.508))
+    (min_thickness 0.254)
+    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
+      (pts
+        (xy 170 80) (xy 155 80) (xy 155 72) (xy 170 72)
+      )
+    )
+    (filled_polygon
+      (pts
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+  )
+)
diff --git a/tests/board_samples/zone-refill.kicad_pcb.ok b/tests/board_samples/zone-refill.kicad_pcb.ok
new file mode 100644
index 00000000..2cba7e7d
--- /dev/null
+++ b/tests/board_samples/zone-refill.kicad_pcb.ok
@@ -0,0 +1,339 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2~bpo10+1)
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 10)
+    (zones 0)
+    (modules 4)
+    (nets 4)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 GND)
+  (net 2 "Net-(C1-Pad1)")
+  (net 3 "Net-(J1-Pad1)")
+
+  (net_class Default "Esta es la clase de red por defecto."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net "Net-(C1-Pad1)")
+    (add_net "Net-(J1-Pad1)")
+  )
+
+  (module Resistor_SMD:R_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC712)
+    (at 161.9375 74 180)
+    (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5EBAD9A3)
+    (attr smd)
+    (fp_text reference R1 (at 0 1.65) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value R (at 0 -1.65) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+    )
+    (fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 "Net-(J1-Pad1)"))
+    (pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 2 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC57B)
+    (at 167 77.54 180)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5EBAC9BE)
+    (fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02_Male (at -4 4.87) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad1)"))
+    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC6B7)
+    (at 157.82 74.85)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5EBAC114)
+    (fp_text reference J1 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02_Male (at -4.82 5.15) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 "Net-(J1-Pad1)"))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC54F)
+    (at 163 77.0625 270)
+    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5EBAE412)
+    (attr smd)
+    (fp_text reference C1 (at 0 1.65 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value C (at 0 -1.65 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+    )
+    (fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 1 GND))
+    (pad 1 smd roundrect (at -0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 2 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 170 80) (end 169 80) (layer Edge.Cuts) (width 0.05) (tstamp 5EBAC92C))
+  (gr_line (start 170 72) (end 170 80) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 155 72) (end 170 72) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 155 80) (end 155 72) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 169 80) (end 155 80) (layer Edge.Cuts) (width 0.05))
+
+  (segment (start 162.39 77.39) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 157.82 77.39) (end 162.39 77.39) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 163.46 77.54) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 167 77.54) (end 163.46 77.54) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 167 75) (end 164 75) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 164 75) (end 163 76) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 164 75) (end 163 74) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 159.7 74) (end 161 74) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 157.82 74.85) (end 158.92 74.85) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 158.92 74.85) (end 159.7 74) (width 0.25) (layer B.Cu) (net 3))
+
+  (zone (net 1) (net_name GND) (layer B.Cu) (tstamp 5EBAC970) (hatch edge 0.508)
+    (connect_pads (clearance 0.508))
+    (min_thickness 0.254)
+    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
+      (pts
+        (xy 170 80) (xy 155 80) (xy 155 72) (xy 170 72)
+      )
+    )
+    (filled_polygon
+      (pts
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+      )
+    )
+  )
+)
diff --git a/tests/board_samples/zone-refill.kicad_pcb.refill b/tests/board_samples/zone-refill.kicad_pcb.refill
new file mode 100644
index 00000000..9f8cd6e4
--- /dev/null
+++ b/tests/board_samples/zone-refill.kicad_pcb.refill
@@ -0,0 +1,352 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2~bpo10+1)
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 10)
+    (zones 0)
+    (modules 4)
+    (nets 4)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 GND)
+  (net 2 "Net-(C1-Pad1)")
+  (net 3 "Net-(J1-Pad1)")
+
+  (net_class Default "Esta es la clase de red por defecto."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net GND)
+    (add_net "Net-(C1-Pad1)")
+    (add_net "Net-(J1-Pad1)")
+  )
+
+  (module Resistor_SMD:R_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC712)
+    (at 161.9375 74 180)
+    (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags resistor)
+    (path /5EBAD9A3)
+    (attr smd)
+    (fp_text reference R1 (at 0 1.65) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value R (at 0 -1.65) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+    )
+    (fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 3 "Net-(J1-Pad1)"))
+    (pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 2 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC57B)
+    (at 167 77.54 180)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5EBAC9BE)
+    (fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02_Male (at -4 4.87) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 "Net-(C1-Pad1)"))
+    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC6B7)
+    (at 157.82 74.85)
+    (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x02 2.54mm single row")
+    (path /5EBAC114)
+    (fp_text reference J1 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Conn_01x02_Male (at -4.82 5.15) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 1.27 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 GND))
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 "Net-(J1-Pad1)"))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Capacitor_SMD:C_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC54F)
+    (at 163 77.0625 270)
+    (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+    (tags capacitor)
+    (path /5EBAE412)
+    (attr smd)
+    (fp_text reference C1 (at 0 1.65 270) (layer B.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text value C (at 0 -1.65 270) (layer B.Fab)
+      (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+    )
+    (fp_text user %R (at 0 0 270) (layer B.Fab)
+      (effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
+    )
+    (fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
+    (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
+    (fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
+    (fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
+    (pad 2 smd roundrect (at 0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 1 GND))
+    (pad 1 smd roundrect (at -0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
+      (net 2 "Net-(C1-Pad1)"))
+    (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 170 80) (end 169 80) (layer Edge.Cuts) (width 0.05) (tstamp 5EBAC92C))
+  (gr_line (start 170 72) (end 170 80) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 155 72) (end 170 72) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 155 80) (end 155 72) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 169 80) (end 155 80) (layer Edge.Cuts) (width 0.05))
+
+  (segment (start 162.39 77.39) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 157.82 77.39) (end 162.39 77.39) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 163.46 77.54) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 167 77.54) (end 163.46 77.54) (width 0.25) (layer B.Cu) (net 1))
+  (segment (start 167 75) (end 164 75) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 164 75) (end 163 76) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 164 75) (end 163 74) (width 0.25) (layer B.Cu) (net 2))
+  (segment (start 159.7 74) (end 161 74) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 157.82 74.85) (end 158.92 74.85) (width 0.25) (layer B.Cu) (net 3))
+  (segment (start 158.92 74.85) (end 159.7 74) (width 0.25) (layer B.Cu) (net 3))
+
+  (zone (net 1) (net_name GND) (layer B.Cu) (tstamp 5EBAC970) (hatch edge 0.508)
+    (connect_pads (clearance 0.508))
+    (min_thickness 0.254)
+    (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
+    (polygon
+      (pts
+        (xy 170 80) (xy 155 80) (xy 155 72) (xy 170 72)
+      )
+    )
+    (filled_polygon
+      (pts
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diff --git a/tests/reference/PCB_Bot.pdf b/tests/reference/PCB_Bot.pdf
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diff --git a/tests/reference/zone-refill-B_Cu.pdf b/tests/reference/zone-refill-B_Cu.pdf
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diff --git a/tests/test_plot/test_pdf.py b/tests/test_plot/test_pdf.py
index 0597d1da..37d65400 100644
--- a/tests/test_plot/test_pdf.py
+++ b/tests/test_plot/test_pdf.py
@@ -29,3 +29,13 @@ def test_pdf():
     ctx.dont_expect_out_file(ctx.get_gerber_job_filename())
 
     ctx.clean_up()
+
+
+def test_pdf_refill():
+    prj = 'zone-refill'
+    ctx = context.TestContext('Plot_PDF_Refill', prj, 'pdf_zone-refill', '')
+    ctx.run()
+
+    b_cu = ctx.get_gerber_filename('B_Cu', '.pdf')
+    ctx.expect_out_file(b_cu)
+    ctx.compare_image(b_cu)
diff --git a/tests/test_plot/test_print_pcb.py b/tests/test_plot/test_print_pcb.py
index ae0e94b9..b4086305 100644
--- a/tests/test_plot/test_print_pcb.py
+++ b/tests/test_plot/test_print_pcb.py
@@ -19,6 +19,7 @@ from utils import context
 
 PDF_DIR = 'Layers'
 PDF_FILE = 'PCB_Top.pdf'
+PDF_FILE_B = 'PCB_Bot.pdf'
 
 
 def test_print_pcb():
@@ -28,3 +29,12 @@ def test_print_pcb():
     # Check all outputs are there
     ctx.expect_out_file(os.path.join(PDF_DIR, PDF_FILE))
     ctx.clean_up()
+
+
+def test_print_pcb_refill():
+    prj = 'zone-refill'
+    ctx = context.TestContext('PrPCB_Refill', prj, 'print_pcb_zone-refill', '')
+    ctx.run()
+
+    ctx.expect_out_file(PDF_FILE_B)
+    ctx.compare_image(PDF_FILE_B)
diff --git a/tests/utils/context.py b/tests/utils/context.py
index f2a1ced8..ff6ebfa7 100644
--- a/tests/utils/context.py
+++ b/tests/utils/context.py
@@ -11,7 +11,8 @@ from pty import openpty
 COVERAGE_SCRIPT = 'python3-coverage'
 KICAD_PCB_EXT = '.kicad_pcb'
 KICAD_SCH_EXT = '.sch'
-REF_DIR = 'N/A'
+REF_DIR = 'tests/reference'
+
 
 MODE_SCH = 1
 MODE_PCB = 0
@@ -57,7 +58,7 @@ class TestContext(object):
     def _get_yaml_name(self, name, yaml_compressed):
         self.yaml_file = os.path.abspath(os.path.join(self._get_yaml_dir(), name+'.kiplot.yaml'))
         if yaml_compressed:
-           self.yaml_file += '.gz'
+            self.yaml_file += '.gz'
         logging.info('YAML file: '+self.yaml_file)
         assert os.path.isfile(self.yaml_file)
 
diff --git a/tests/yaml_samples/pdf_zone-refill.kiplot.yaml b/tests/yaml_samples/pdf_zone-refill.kiplot.yaml
new file mode 100644
index 00000000..c1ca79a8
--- /dev/null
+++ b/tests/yaml_samples/pdf_zone-refill.kiplot.yaml
@@ -0,0 +1,31 @@
+kiplot:
+  version: 1
+
+preflight:
+  check_zone_fills: true
+
+outputs:
+  - name: PDF
+    comment: "PDF files"
+    type: pdf
+    dir: .
+    options:
+      exclude_edge_layer: false
+      exclude_pads_from_silkscreen: false
+      use_aux_axis_as_origin: false
+      plot_sheet_reference: false
+      plot_footprint_refs: true
+      plot_footprint_values: true
+      force_plot_invisible_refs_vals: false
+      tent_vias: true
+      check_zone_fills: true
+
+      # PDF options
+      drill_marks: small
+      mirror_plot: false
+      negative_plot: false
+      line_width: 0.01
+    layers:
+      - layer: B.Cu
+        suffix: B_Cu
+
diff --git a/tests/yaml_samples/print_pcb_zone-refill.kiplot.yaml b/tests/yaml_samples/print_pcb_zone-refill.kiplot.yaml
new file mode 100644
index 00000000..71b4e681
--- /dev/null
+++ b/tests/yaml_samples/print_pcb_zone-refill.kiplot.yaml
@@ -0,0 +1,17 @@
+# Example KiPlot config file
+kiplot:
+  version: 1
+
+preflight:
+  check_zone_fills: true
+
+outputs:
+  - name: 'print_front'
+    comment: "Print B.Cu (filling zones)"
+    type: pdf_pcb_print
+    dir: .
+    options:
+      output_name: PCB_Bot.pdf
+    layers:
+      - layer: B.Cu
+