[Sub-PCBs][Test] Enabled KiCad 5 tests
- Fixed new drill coordinates in test - Renamed some YAML files
This commit is contained in:
Salvador E. Tropea
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27247c17b6
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update=St 1. dubna 2020, 17:02:35 CEST
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=
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ViaDiameter1=0.8
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ViaDiameter3=1.4
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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<text x="58464.6" y="45472.4" textLength="3776.9" font-size="1049.87" lengthAdjust="spacingAndGlyphs" text-anchor="middle" opacity="0">MINUS</text>
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<text x="58661.4" y="38090.6" textLength="3204.35" font-size="1049.87" lengthAdjust="spacingAndGlyphs" text-anchor="middle" opacity="0">PLUS</text>
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</g>
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|
After Width: | Height: | Size: 36 KiB |
|
|
@ -10,7 +10,6 @@ pytest-3 --log-cli-level debug
|
||||||
|
|
||||||
"""
|
"""
|
||||||
|
|
||||||
import pytest
|
|
||||||
import os
|
import os
|
||||||
import sys
|
import sys
|
||||||
from . import context
|
from . import context
|
||||||
|
|
@ -102,7 +101,6 @@ def test_drill_legacy_s_3Rs(test_dir):
|
||||||
do_3Rs(test_dir, 'drill_legacy_s', False, True)
|
do_3Rs(test_dir, 'drill_legacy_s', False, True)
|
||||||
|
|
||||||
|
|
||||||
@pytest.mark.skipif(context.ki5(), reason="KiKit currently supports KiCad 6 only")
|
|
||||||
def test_drill_sub_pcb_bp(test_dir):
|
def test_drill_sub_pcb_bp(test_dir):
|
||||||
""" Test a multiboard example """
|
""" Test a multiboard example """
|
||||||
prj = 'batteryPack'
|
prj = 'batteryPack'
|
||||||
|
|
@ -111,6 +109,6 @@ def test_drill_sub_pcb_bp(test_dir):
|
||||||
# Check all outputs are there
|
# Check all outputs are there
|
||||||
fname = prj+'-drill_connector.drl'
|
fname = prj+'-drill_connector.drl'
|
||||||
# ctx.search_in_file_d(fname, ['X29.75Y-28.09', 'T3C3.200']) KiKit
|
# ctx.search_in_file_d(fname, ['X29.75Y-28.09', 'T3C3.200']) KiKit
|
||||||
ctx.search_in_file_d(fname, ['X120.0Y-73.0', 'T3C3.200']) # Currently us
|
ctx.search_in_file_d(fname, ['X137.5Y-102.0', 'T3C3.200']) # Currently us
|
||||||
ctx.search_not_in_file_d(fname, ['X189.0Y-59.0', 'T1C0.400'])
|
ctx.search_not_in_file_d(fname, ['X189.0Y-59.0', 'T1C0.400'])
|
||||||
ctx.clean_up(keep_project=True)
|
ctx.clean_up(keep_project=True)
|
||||||
|
|
|
||||||
|
|
@ -1521,11 +1521,10 @@ def test_copy_files_2(test_dir):
|
||||||
ctx.clean_up()
|
ctx.clean_up()
|
||||||
|
|
||||||
|
|
||||||
@pytest.mark.skipif(context.ki5(), reason="KiKit currently supports KiCad 6 only")
|
|
||||||
def test_sub_pcb_bp(test_dir):
|
def test_sub_pcb_bp(test_dir):
|
||||||
""" Test a multiboard example """
|
""" Test a multiboard example """
|
||||||
prj = 'batteryPack'
|
prj = 'batteryPack'
|
||||||
ctx = context.TestContext(test_dir, prj, 'pcb_variant_subpc_bp', '')
|
ctx = context.TestContext(test_dir, prj, 'pcb_variant_sub_pcb_bp', '')
|
||||||
ctx.run()
|
ctx.run()
|
||||||
# Check all outputs are there
|
# Check all outputs are there
|
||||||
fname_b = prj+'-variant_'
|
fname_b = prj+'-variant_'
|
||||||
|
|
|
||||||
|
|
@ -6,7 +6,6 @@ pytest-3 --log-cli-level debug
|
||||||
"""
|
"""
|
||||||
import coverage
|
import coverage
|
||||||
import logging
|
import logging
|
||||||
import pytest
|
|
||||||
from shutil import which
|
from shutil import which
|
||||||
from os import access
|
from os import access
|
||||||
from . import context
|
from . import context
|
||||||
|
|
@ -181,11 +180,10 @@ def test_pcbdraw_variant_3(test_dir):
|
||||||
ctx.clean_up(keep_project=True)
|
ctx.clean_up(keep_project=True)
|
||||||
|
|
||||||
|
|
||||||
@pytest.mark.skipif(context.ki5(), reason="KiKit currently supports KiCad 6 only")
|
|
||||||
def test_pcbdraw_sub_pcb_bp(test_dir):
|
def test_pcbdraw_sub_pcb_bp(test_dir):
|
||||||
""" Test a multiboard example """
|
""" Test a multiboard example """
|
||||||
prj = 'batteryPack'
|
prj = 'batteryPack'
|
||||||
ctx = context.TestContext(test_dir, prj, 'pcbdraw_subpc_bp', '')
|
ctx = context.TestContext(test_dir, prj, 'pcbdraw_sub_pcb_bp', '')
|
||||||
ctx.run()
|
ctx.run()
|
||||||
# Check all outputs are there
|
# Check all outputs are there
|
||||||
fname_b = prj+'-top_'
|
fname_b = prj+'-top_'
|
||||||
|
|
|
||||||
|
|
@ -29,6 +29,7 @@ variants:
|
||||||
tly: 52
|
tly: 52
|
||||||
brx: 146
|
brx: 146
|
||||||
bry: 88
|
bry: 88
|
||||||
|
tolerance: 1
|
||||||
|
|
||||||
outputs:
|
outputs:
|
||||||
- name: 'pcb_charger'
|
- name: 'pcb_charger'
|
||||||
|
|
@ -27,6 +27,7 @@ variants:
|
||||||
tly: 52
|
tly: 52
|
||||||
brx: 146
|
brx: 146
|
||||||
bry: 88
|
bry: 88
|
||||||
|
tolerance: 1
|
||||||
|
|
||||||
outputs:
|
outputs:
|
||||||
- name: draw_charger
|
- name: draw_charger
|
||||||
Loading…
Reference in New Issue