Salvador E. Tropea
parent
4d5220006f
commit
278de8fb16
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@ -60,6 +60,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- Support for `--subst-models` option for KiCad 6's kicad2step. (#137)
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- Added global options to define the PCB details (`pcb_material`,
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`solder_mask_color`, `silk_screen_color` and `pcb_finish`)
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- Report generation (for design house) (#93)
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### Changed
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- Internal BoM: now components with different Tolerance, Voltage, Current
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@ -1,3 +1,4 @@
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include MANIFEST.in
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include LICENSE
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include README.md
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include kibot/report_templates/*.txt
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19
README.md
19
README.md
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@ -1771,6 +1771,25 @@ Next time you need this list just use an alias, like this:
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- `output_id`: [string=''] Text to use for the %I expansion content. To differentiate variations of this output.
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- `run_by_default`: [boolean=true] When enabled this output will be created when no specific outputs are requested.
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* Design report
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* Type: `report`
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* Description: Generates a report about the design.
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Mainly oriented to be sent to the manufacturer or check PCB details.
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* Valid keys:
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- `comment`: [string=''] A comment for documentation purposes.
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- `dir`: [string='./'] Output directory for the generated files. If it starts with `+` the rest is concatenated to the default dir.
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- `disable_run_by_default`: [string|boolean] Use it to disable the `run_by_default` status of other output.
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Useful when this output extends another and you don't want to generate the original.
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Use the boolean true value to disable the output you are extending.
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- `extends`: [string=''] Copy the `options` section from the indicated output.
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- `name`: [string=''] Used to identify this particular output definition.
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- `options`: [dict] Options for the `report` output.
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* Valid keys:
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- `output`: [string='%f-%i%v.%x'] Output file name (%i='report', %x='txt'). Affected by global options.
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- `template`: [string='full'] Name for one of the internal templates (full, simple) or a custom template file.
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- `output_id`: [string=''] Text to use for the %I expansion content. To differentiate variations of this output.
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- `run_by_default`: [boolean=true] When enabled this output will be created when no specific outputs are requested.
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* Schematic with variant generator
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* Type: `sch_variant`
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* Description: Creates a copy of the schematic with all the filters and variants applied.
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@ -1232,6 +1232,18 @@ outputs:
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# Same result as using the mouse wheel in the 3D viewer
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zoom: 0
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# Design report:
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# Mainly oriented to be sent to the manufacturer or check PCB details.
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- name: 'report_example'
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comment: 'Generates a report about the design.'
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type: 'report'
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dir: 'Example/report_dir'
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options:
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# [string='%f-%i%v.%x'] Output file name (%i='report', %x='txt'). Affected by global options
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output: '%f-%i%v.%x'
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# [string='full'] Name for one of the internal templates (full, simple) or a custom template file
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template: 'full'
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# Schematic with variant generator:
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# This copy isn't intended for development.
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# Is just a tweaked version of the original where you can look at the results.
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@ -0,0 +1,464 @@
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# -*- coding: utf-8 -*-
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# Copyright (c) 2022 Salvador E. Tropea
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# Copyright (c) 2022 Instituto Nacional de Tecnología Industrial
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# License: GPL-3.0
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# Project: KiBot (formerly KiPlot)
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import os
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import re
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import pcbnew
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from .gs import GS
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from .misc import UI_SMD, UI_VIRTUAL, MOD_THROUGH_HOLE, MOD_SMD, MOD_EXCLUDE_FROM_POS_FILES
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from .out_base import BaseOptions
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from .error import KiPlotConfigurationError
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from .macros import macros, document, output_class # noqa: F401
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from . import log
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logger = log.get_logger()
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INF = float('inf')
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def do_round(v, dig):
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v = round(v+1e-9, dig)
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return v if dig else int(v)
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def to_mm(iu, dig=2):
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""" KiCad Internal Units to millimeters """
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return do_round(iu/pcbnew.IU_PER_MM, dig)
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def to_mils(iu, dig=0):
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""" KiCad Internal Units to mils (1/1000 inch) """
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return do_round(iu/pcbnew.IU_PER_MILS, dig)
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def to_inches(iu, dig=2):
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""" KiCad Internal Units to inches """
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return do_round(iu/(pcbnew.IU_PER_MILS*1000), dig)
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def get_class_index(val, lst):
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""" Used to search in an Eurocircuits class vector.
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Returns the first match that is >= to val. """
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val = to_mm(val, 3)
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for c, v in enumerate(lst):
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if val >= v:
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return c
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return c+1
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def get_pattern_class(track, clearance, oar):
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""" Returns the Eurocircuits Pattern class for a track width, clearance and OAR """
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c1 = (0.25, 0.2, 0.175, 0.150, 0.125, 0.1, 0.09)
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c2 = (0.2, 0.15, 0.15, 0.125, 0.125, 0.1, 0.1)
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ct = get_class_index(track, c1)
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cc = get_class_index(clearance, c1)
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co = get_class_index(oar, c2)
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cf = max(ct, max(cc, co))
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return cf + 3
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def get_drill_class(via_drill):
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""" Returns the Eurocircuits Drill class for a drill size.
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This is the real (tool) size. """
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c3 = (0.6, 0.45, 0.35, 0.25, 0.2)
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cd = get_class_index(via_drill, c3)
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return chr(ord('A') + cd)
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def to_top_bottom(front, bottom):
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""" Returns a text indicating if the feature is in top/bottom layers """
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if front and bottom:
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return "TOP / BOTTOM"
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elif front:
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return "TOP"
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elif bottom:
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return "BOTTOM"
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return "NONE"
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def to_smd_tht(smd, tht):
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""" Returns a text indicating if the components are SMD/THT """
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if smd and tht:
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return "SMD + THT"
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elif smd:
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return "SMD"
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elif tht:
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return "THT"
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return "NONE"
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class ReportOptions(BaseOptions):
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def __init__(self):
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with document:
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self.output = GS.def_global_output
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""" Output file name (%i='report', %x='txt') """
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self.template = 'full'
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""" Name for one of the internal templates (full, simple) or a custom template file """
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super().__init__()
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self._expand_id = 'report'
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self._expand_ext = 'txt'
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self._mm_digits = 2
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self._mils_digits = 0
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self._in_digits = 2
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def config(self, parent):
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super().config(parent)
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if self.template.lower() in ('full', 'simple'):
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self.template = os.path.abspath(os.path.join(os.path.dirname(__file__), 'report_templates',
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'report_'+self.template.lower()+'.txt'))
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if not os.path.isfile(self.template):
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raise KiPlotConfigurationError("Missing report template: `{}`".format(self.template))
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def do_replacements(self, line, defined):
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""" Replace ${VAR} patterns """
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for var in re.findall(r'\$\{([^\s\}]+)\}', line):
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if var[0] == '_':
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# Prevent access to internal data
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continue
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units = None
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var_ori = var
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if var.endswith('_mm'):
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units = to_mm
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digits = self._mm_digits
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var = var[:-3]
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elif var.endswith('_in'):
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units = to_inches
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digits = self._in_digits
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var = var[:-3]
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elif var.endswith('_mils'):
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units = to_mils
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digits = self._mils_digits
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var = var[:-5]
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if var in defined:
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val = defined[var]
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if val == INF:
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val = 'N/A'
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elif units is not None and isinstance(val, (int, float)):
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val = units(val, digits)
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line = line.replace('${'+var_ori+'}', str(val))
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else:
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print('Error: Unable to expand `{}`'.format(var))
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return line
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def context_defined_tracks(self, line):
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""" Replace iterator for the `defined_tracks` context """
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text = ''
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for t in sorted(self._track_sizes):
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if not t:
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continue # KiCad 6
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text += self.do_replacements(line, {'track': t})
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return text
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def context_used_tracks(self, line):
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""" Replace iterator for the `used_tracks` context """
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text = ''
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for t in sorted(self._tracks_m.keys()):
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text += self.do_replacements(line, {'track': t, 'count': self._tracks_m[t],
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'defined': 'yes' if t in self._tracks_defined else 'no'})
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return text
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def context_defined_vias(self, line):
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""" Replace iterator for the `defined_vias` context """
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text = ''
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for v in self._via_sizes_sorted:
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text += self.do_replacements(line, {'pad': v[1], 'drill': v[0]})
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return text
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def context_used_vias(self, line):
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""" Replace iterator for the `used_vias` context """
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text = ''
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for v in self._vias_m:
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d = v[1]
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h = v[0]
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aspect = round(self.thickness/d, 1)
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# IPC-2222 Table 9.4
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producibility_level = 'C'
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if aspect < 9:
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if aspect < 5:
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producibility_level = 'A'
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else:
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producibility_level = 'B'
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defined = {'pad': v[1], 'drill': v[0]}
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defined['count'] = self._vias[v]
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defined['aspect'] = aspect
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defined['producibility_level'] = producibility_level
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defined['defined'] = 'yes' if (h, d) in self._vias_defined else 'no'
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text += self.do_replacements(line, defined)
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return text
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def context_hole_sizes_no_vias(self, line):
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""" Replace iterator for the `hole_sizes_no_vias` context """
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text = ''
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for d in sorted(self._drills.keys()):
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text += self.do_replacements(line, {'drill': d, 'count': self._drills[d]})
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return text
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@staticmethod
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def is_pure_smd_5(m):
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return m.GetAttributes() == UI_SMD
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@staticmethod
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def is_pure_smd_6(m):
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return m.GetAttributes() & (MOD_THROUGH_HOLE | MOD_SMD) == MOD_SMD
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@staticmethod
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def is_not_virtual_5(m):
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return m.GetAttributes() != UI_VIRTUAL
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@staticmethod
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def is_not_virtual_6(m):
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return not (m.GetAttributes() & MOD_EXCLUDE_FROM_POS_FILES)
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def get_attr_tests(self):
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if GS.ki5():
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return self.is_pure_smd_5, self.is_not_virtual_5
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return self.is_pure_smd_6, self.is_not_virtual_6
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def meassure_pcb(self, board):
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edge_layer = board.GetLayerID('Edge.Cuts')
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x1 = y1 = x2 = y2 = None
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draw_type = 'DRAWSEGMENT' if GS.ki5() else 'PCB_SHAPE'
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for d in board.GetDrawings():
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if d.GetClass() == draw_type and d.GetLayer() == edge_layer:
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if x1 is None:
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p = d.GetStart()
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x1 = x2 = p.x
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y1 = y2 = p.y
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for p in [d.GetStart(), d.GetEnd()]:
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x2 = max(x2, p.x)
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y2 = max(y2, p.y)
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x1 = min(x1, p.x)
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y1 = min(y1, p.y)
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if x1 is None:
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self.bb_w = self.bb_h = INF
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else:
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self.bb_w = x2-x1
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self.bb_h = y2-y1
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def collect_data(self, board):
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ds = board.GetDesignSettings()
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###########################################################
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# Board size
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###########################################################
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# The value returned by ComputeBoundingBox(True) adds the drawing width!
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bb = board.ComputeBoundingBox(True)
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self.bb_w_d = bb.GetWidth()
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self.bb_h_d = bb.GetHeight()
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self.meassure_pcb(board)
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###########################################################
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# Board thickness
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###########################################################
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self.thickness = ds.GetBoardThickness()
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###########################################################
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# Number of layers
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###########################################################
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self.layers = ds.GetCopperLayerCount()
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###########################################################
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# Solder mask layers
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###########################################################
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fmask = board.IsLayerEnabled(board.GetLayerID('F.Mask'))
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bmask = board.IsLayerEnabled(board.GetLayerID('B.Mask'))
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self.solder_mask = to_top_bottom(fmask, bmask)
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###########################################################
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# Silk screen
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###########################################################
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fsilk = board.IsLayerEnabled(board.GetLayerID('F.SilkS'))
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bsilk = board.IsLayerEnabled(board.GetLayerID('B.SilkS'))
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self.silk_screen = to_top_bottom(fsilk, bsilk)
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###########################################################
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# Clearance
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###########################################################
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self.clearance = ds.GetSmallestClearanceValue()
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# This seems to be bogus:
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# h2h = ds.m_HoleToHoleMin
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###########################################################
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# Track width (min)
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###########################################################
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self.track_d = ds.m_TrackMinWidth
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tracks = board.GetTracks()
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self.oar_vias = self.track = INF
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self._vias = {}
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self._tracks_m = {}
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track_type = 'TRACK' if GS.ki5() else 'PCB_TRACK'
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via_type = 'VIA' if GS.ki5() else 'PCB_VIA'
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for t in tracks:
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tclass = t.GetClass()
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if tclass == track_type:
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w = t.GetWidth()
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self.track = min(w, self.track)
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self._tracks_m[w] = self._tracks_m.get(w, 0) + 1
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elif tclass == via_type:
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via = t.Cast()
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via_id = (via.GetDrill(), via.GetWidth())
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self._vias[via_id] = self._vias.get(via_id, 0) + 1
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self.oar_vias = min(self.oar_vias, via_id[1] - via_id[0])
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self.track_min = min(self.track_d, self.track)
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###########################################################
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# Drill (min)
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###########################################################
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modules = board.GetModules() if GS.ki5() else board.GetFootprints()
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self._drills = {}
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self._drills_oval = {}
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self.oar_pads = self.pad_drill = INF
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self.slot = INF
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self.top_smd = self.top_tht = self.bot_smd = self.bot_tht = 0
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top_layer = board.GetLayerID('F.Cu')
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bottom_layer = board.GetLayerID('B.Cu')
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is_pure_smd, is_not_virtual = self.get_attr_tests()
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for m in modules:
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layer = m.GetLayer()
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if layer == top_layer:
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if is_pure_smd(m):
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self.top_smd += 1
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elif is_not_virtual(m):
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self.top_tht += 1
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elif layer == bottom_layer:
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if is_pure_smd(m):
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self.bot_smd += 1
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elif is_not_virtual(m):
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self.bot_tht += 1
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pads = m.Pads()
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for pad in pads:
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dr = pad.GetDrillSize()
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if not dr.x:
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continue
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self.pad_drill = min(dr.x, self.pad_drill)
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self.pad_drill = min(dr.y, self.pad_drill)
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if dr.x == dr.y:
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self._drills[dr.x] = self._drills.get(dr.x, 0) + 1
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else:
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if dr.x < dr.y:
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m = (dr.x, dr.y)
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else:
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m = (dr.y, dr.x)
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self._drills_oval[m] = self._drills_oval.get(m, 0) + 1
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self.slot = min(self.slot, m[0])
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# print('{} @ {}'.format(dr, pad.GetPosition()))
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pad_sz = pad.GetSize()
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oar_x = pad_sz.x - dr.x
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oar_y = pad_sz.y - dr.y
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oar_t = min(oar_x, oar_y)
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if oar_t:
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self.oar_pads = min(self.oar_pads, oar_t)
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self._vias_m = list(sorted(self._vias.keys()))
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# Via Pad size
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self.via_pad_d = ds.m_ViasMinSize
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self.via_pad = self._vias_m[0][1]
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self.via_pad_min = min(self.via_pad_d, self.via_pad)
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# Via Drill size
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self.via_drill_d = ds.m_ViasMinDrill if GS.ki5() else ds.m_MinThroughDrill
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self.via_drill = self._vias_m[0][0]
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self.via_drill_min = min(self.via_drill_d, self.via_drill)
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# Via Drill size minus 0.1 mm
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self.via_drill_1_d = self.via_drill_d - pcbnew.IU_PER_MM/10
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self.via_drill_1 = self.via_drill - pcbnew.IU_PER_MM/10
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self.via_drill_1_min = self.via_drill_min - pcbnew.IU_PER_MM/10
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# Pad Drill
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# No minimum defined
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self.pad_drill_min = self.pad_drill if GS.ki5() else ds.m_MinThroughDrill
|
||||
# Pad Drill size minus 0.1 mm
|
||||
self.pad_drill_1 = self.pad_drill_1_min = self.pad_drill - pcbnew.IU_PER_MM/10
|
||||
# Drill overall
|
||||
self.drill_d = min(self.via_drill_d, self.pad_drill)
|
||||
self.drill = min(self.via_drill, self.pad_drill)
|
||||
self.drill_min = min(self.via_drill_min, self.pad_drill_min)
|
||||
# Drill overall size minus 0.1 mm
|
||||
self.drill_1_d = self.drill_d - pcbnew.IU_PER_MM/10
|
||||
self.drill_1 = self.drill - pcbnew.IU_PER_MM/10
|
||||
self.drill_1_min = self.drill_min - pcbnew.IU_PER_MM/10
|
||||
self.top_comp_type = to_smd_tht(self.top_smd, self.top_tht)
|
||||
self.bot_comp_type = to_smd_tht(self.bot_smd, self.bot_tht)
|
||||
###########################################################
|
||||
# Vias
|
||||
###########################################################
|
||||
self.micro_vias = 'yes' if ds.m_MicroViasAllowed else 'no'
|
||||
self.blind_vias = 'yes' if ds.m_BlindBuriedViaAllowed else 'no'
|
||||
self.uvia_pad = ds.m_MicroViasMinSize
|
||||
self.uvia_drill = ds.m_MicroViasMinDrill
|
||||
via_sizes = board.GetViasDimensionsList()
|
||||
self._vias_defined = set()
|
||||
self._via_sizes_sorted = []
|
||||
self.oar_vias_d = INF
|
||||
for v in sorted(via_sizes, key=lambda x: (x.m_Diameter, x.m_Drill)):
|
||||
d = v.m_Diameter
|
||||
h = v.m_Drill
|
||||
if not d and not h:
|
||||
continue # KiCad 6
|
||||
self.oar_vias_d = min(self.oar_vias_d, d - h)
|
||||
self._vias_defined.add((h, d))
|
||||
self._via_sizes_sorted.append((h, d))
|
||||
###########################################################
|
||||
# Outer Annular Ring
|
||||
###########################################################
|
||||
self.oar_pads_min = self.oar_pads
|
||||
self.oar_d = min(self.oar_vias_d, self.oar_pads)
|
||||
self.oar = min(self.oar_vias, self.oar_pads)
|
||||
self.oar_min = min(self.oar_d, self.oar)
|
||||
self.oar_vias_min = min(self.oar_vias_d, self.oar_vias)
|
||||
###########################################################
|
||||
# Eurocircuits class
|
||||
# https://www.eurocircuits.com/pcb-design-guidelines-classification/
|
||||
###########################################################
|
||||
# Pattern class
|
||||
self.pattern_class_min = get_pattern_class(self.track_min, self.clearance, self.oar_min)
|
||||
self.pattern_class = get_pattern_class(self.track, self.clearance, self.oar)
|
||||
self.pattern_class_d = get_pattern_class(self.track_d, self.clearance, self.oar_d)
|
||||
# Drill class
|
||||
self.drill_class_min = get_drill_class(self.via_drill_min)
|
||||
self.drill_class = get_drill_class(self.via_drill)
|
||||
self.drill_class_d = get_drill_class(self.via_drill_d)
|
||||
###########################################################
|
||||
# General stats
|
||||
###########################################################
|
||||
self._track_sizes = board.GetTrackWidthList()
|
||||
self._tracks_defined = set(self._track_sizes)
|
||||
|
||||
def do_template(self, template_file, output_file):
|
||||
text = ''
|
||||
logger.debug("Report template: `{}`".format(template_file))
|
||||
with open(template_file, "rt") as f:
|
||||
for line in f:
|
||||
done = False
|
||||
if line[0] == '#' and ':' in line:
|
||||
context = line[1:].split(':')[0]
|
||||
logger.debug("Report context: `{}`".format(context))
|
||||
try:
|
||||
# Contexts are members called context_*
|
||||
line = getattr(self, 'context_'+context)(line[len(context)+2:])
|
||||
done = True
|
||||
except AttributeError:
|
||||
pass
|
||||
if not done:
|
||||
raise KiPlotConfigurationError("Unknown context: `{}`".format(context))
|
||||
if not done:
|
||||
# Just replace using any data member (_* excluded)
|
||||
line = self.do_replacements(line, self.__dict__)
|
||||
text += line
|
||||
logger.debug("Report output: `{}`".format(output_file))
|
||||
with open(output_file, "wt") as f:
|
||||
f.write(text)
|
||||
|
||||
def get_targets(self, out_dir):
|
||||
return [self._parent.expand_filename(out_dir, self.output)]
|
||||
|
||||
def run(self, fname):
|
||||
self.pcb_material = GS.global_pcb_material
|
||||
self.solder_mask_color = GS.global_solder_mask_color
|
||||
self.silk_screen_color = GS.global_silk_screen_color
|
||||
self.pcb_finish = GS.global_pcb_finish
|
||||
self.collect_data(GS.board)
|
||||
self.do_template(self.template, fname)
|
||||
|
||||
|
||||
@output_class
|
||||
class Report(BaseOutput): # noqa: F821
|
||||
""" Design report
|
||||
Generates a report about the design.
|
||||
Mainly oriented to be sent to the manufacturer or check PCB details. """
|
||||
def __init__(self):
|
||||
super().__init__()
|
||||
with document:
|
||||
self.options = ReportOptions
|
||||
""" [dict] Options for the `report` output """
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
# PCB
|
||||
|
||||
Board size: ${bb_w_mm}x${bb_h_mm} mm (${bb_w_in}x${bb_h_in} inches)
|
||||
- This is the size of the rectangle that contains the board
|
||||
- Thickness: ${thickness_mm} mm (${thickness_mils} mils)
|
||||
- Material: ${pcb_material}
|
||||
- Finish: ${pcb_finish}
|
||||
- Layers: ${layers}
|
||||
Solder mask: ${solder_mask}
|
||||
- Color: ${solder_mask_color}
|
||||
Silk screen: ${silk_screen}
|
||||
- Color: ${silk_screen_color}
|
||||
|
||||
|
||||
# Important sizes
|
||||
|
||||
Clearance: ${clearance_mm} mm (${clearance_mils} mils)
|
||||
Track width: ${track_mm} mm (${track_mils} mils)
|
||||
- By design rules: ${track_d_mm} mm (${track_d_mils} mils)
|
||||
Drill: ${drill_mm} mm (${drill_mils} mils)
|
||||
- Vias: ${via_drill_mm} mm (${via_drill_mils} mils) [Design: ${via_drill_d_mm} mm (${via_drill_d_mils} mils)]
|
||||
- Pads: ${pad_drill_mm} mm (${pad_drill_mils} mils)
|
||||
Via: ${via_pad_mm}/${via_drill_mm} mm (${via_pad_mils}/${via_drill_mils} mils)
|
||||
- By design rules: ${via_pad_d_mm}/${via_drill_d_mm} mm (${via_pad_d_mils}/${via_drill_d_mils} mils)
|
||||
- Micro via: ${micro_vias} [${uvia_pad_mm}/${uvia_drill_mm} mm (${uvia_pad_mils}/${uvia_drill_mils} mils)]
|
||||
- Burried/blind via: ${blind_vias}
|
||||
Outer Annular Ring: ${oar_mm} mm (${oar_mils} mils)
|
||||
- By design rules: ${oar_d_mm} mm (${oar_d_mils} mils)
|
||||
|
||||
Eurocircuits class: ${pattern_class}${drill_class}
|
||||
|
||||
|
||||
# General stats
|
||||
|
||||
Components count: (SMD/THT)
|
||||
- Top: ${top_smd}/${top_tht} (${top_comp_type})
|
||||
- Bottom: ${bot_smd}/${bot_tht} (${bot_comp_type})
|
||||
|
||||
Defined tracks:
|
||||
#defined_tracks:- ${track_mm} mm (${track_mils} mils)
|
||||
|
||||
Used tracks:
|
||||
#used_tracks:- ${track_mm} mm (${track_mils} mils) (${count}) defined: ${defined}
|
||||
|
||||
Defined vias:
|
||||
#defined_vias:- ${pad_mm}/${drill_mm} mm (${pad_mils}/${drill_mils} mils)
|
||||
|
||||
Used vias:
|
||||
#used_vias:- ${pad_mm}/${drill_mm} mm (${pad_mils}/${drill_mils} mils) (Count: ${count}, Aspect: ${aspect} ${producibility_level}) defined: ${defined}
|
||||
|
||||
Holes (excluding vias):
|
||||
#hole_sizes_no_vias:- ${drill_mm} mm (${drill_mils} mils) (${count})
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
PCB Specifications:
|
||||
Size:
|
||||
- ${bb_w_mm}x${bb_h_mm} mm
|
||||
|
||||
Class: ${pattern_class}${drill_class}
|
||||
Track width: ≥ ${track_mm} mm
|
||||
Insulation distance: ≥ ${clearance_mm} mm
|
||||
Minimum drill size: ≥ ${drill_mm} mm (finished metalized hole: ${drill_1_mm} mm)
|
||||
Minimum slot width: ≥ ${slot_mm} mm
|
||||
Ring collar: ≥ ${oar_mm} mm
|
||||
|
||||
|
||||
Materials:
|
||||
- ${pcb_material}, ${thickness_mm} mm
|
||||
- ${pcb_finish}
|
||||
- ${layers} layers
|
||||
- 35 µm copper thickness
|
||||
|
||||
Solder mask:
|
||||
- ${solder_mask}
|
||||
- ${solder_mask_color}
|
||||
|
||||
Marking:
|
||||
- ${silk_screen} screen printing
|
||||
- Silk: ${silk_screen_color}
|
||||
|
||||
Other markings:
|
||||
- ROHS / UL / Date - Yes if available
|
||||
1
setup.py
1
setup.py
|
|
@ -21,6 +21,7 @@ setup(name='kibot',
|
|||
packages=find_packages(),
|
||||
scripts=['src/kibot', 'src/kiplot'],
|
||||
install_requires=['kiauto', 'pyyaml', 'xlsxwriter', 'colorama', 'requests', 'qrcodegen'],
|
||||
include_package_data=True,
|
||||
classifiers=['Development Status :: 5 - Production/Stable',
|
||||
'Environment :: Console',
|
||||
'Intended Audience :: Developers',
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
|
|||
# PCB
|
||||
|
||||
Board size: 59.69x48.26 mm (2.35x1.9 inches)
|
||||
- This is the size of the rectangle that contains the board
|
||||
- Thickness: 1.6 mm (63 mils)
|
||||
- Material: FR4
|
||||
- Finish: ENIG
|
||||
- Layers: 4
|
||||
Solder mask: TOP / BOTTOM
|
||||
- Color: blue
|
||||
Silk screen: TOP / BOTTOM
|
||||
- Color: white
|
||||
|
||||
|
||||
# Important sizes
|
||||
|
||||
Clearance: 0.15 mm (6 mils)
|
||||
Track width: 0.15 mm (6 mils)
|
||||
- By design rules: 0.13 mm (5 mils)
|
||||
Drill: 0.25 mm (10 mils)
|
||||
- Vias: 0.25 mm (10 mils) [Design: 0.2 mm (8 mils)]
|
||||
- Pads: 0.6 mm (24 mils)
|
||||
Via: 0.51/0.25 mm (20/10 mils)
|
||||
- By design rules: 0.46/0.2 mm (18/8 mils)
|
||||
- Micro via: no [0.2/0.1 mm (8/4 mils)]
|
||||
- Burried/blind via: no
|
||||
Outer Annular Ring: 0.25 mm (10 mils)
|
||||
- By design rules: 0.25 mm (10 mils)
|
||||
|
||||
Eurocircuits class: 6D
|
||||
|
||||
|
||||
# General stats
|
||||
|
||||
Components count: (SMD/THT)
|
||||
- Top: 61/12 (SMD + THT)
|
||||
- Bottom: 0/0 (NONE)
|
||||
|
||||
Defined tracks:
|
||||
- 0.15 mm (6 mils)
|
||||
- 0.25 mm (10 mils)
|
||||
- 0.3 mm (12 mils)
|
||||
- 0.64 mm (25 mils)
|
||||
|
||||
Used tracks:
|
||||
- 0.15 mm (6 mils) (276) defined: yes
|
||||
- 0.3 mm (12 mils) (11) defined: yes
|
||||
- 0.64 mm (25 mils) (175) defined: yes
|
||||
|
||||
Defined vias:
|
||||
- 0.51/0.25 mm (20/10 mils)
|
||||
- 0.8/0.4 mm (31/16 mils)
|
||||
- 0.89/0.51 mm (35/20 mils)
|
||||
|
||||
Used vias:
|
||||
- 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes
|
||||
- 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes
|
||||
|
||||
Holes (excluding vias):
|
||||
- 0.8 mm (31 mils) (4)
|
||||
- 0.85 mm (33 mils) (2)
|
||||
- 0.95 mm (37 mils) (3)
|
||||
- 1.2 mm (47 mils) (20)
|
||||
- 3.2 mm (126 mils) (4)
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
PCB Specifications:
|
||||
Size:
|
||||
- 59.69x48.26 mm
|
||||
|
||||
Class: 6D
|
||||
Track width: ≥ 0.15 mm
|
||||
Insulation distance: ≥ 0.15 mm
|
||||
Minimum drill size: ≥ 0.25 mm (finished metalized hole: 0.15 mm)
|
||||
Minimum slot width: ≥ 0.6 mm
|
||||
Ring collar: ≥ 0.25 mm
|
||||
|
||||
|
||||
Materials:
|
||||
- FR4, 1.6 mm
|
||||
- ENIG
|
||||
- 4 layers
|
||||
- 35 µm copper thickness
|
||||
|
||||
Solder mask:
|
||||
- TOP / BOTTOM
|
||||
- blue
|
||||
|
||||
Marking:
|
||||
- TOP / BOTTOM screen printing
|
||||
- Silk: white
|
||||
|
||||
Other markings:
|
||||
- ROHS / UL / Date - Yes if available
|
||||
|
|
@ -0,0 +1 @@
|
|||
../5_1_6/light_control-report.txt
|
||||
|
|
@ -0,0 +1 @@
|
|||
../5_1_6/light_control-report_simple.txt
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
# PCB
|
||||
|
||||
Board size: 59.69x48.26 mm (2.35x1.9 inches)
|
||||
- This is the size of the rectangle that contains the board
|
||||
- Thickness: 1.6 mm (63 mils)
|
||||
- Material: FR4
|
||||
- Finish: ENIG
|
||||
- Layers: 4
|
||||
Solder mask: TOP / BOTTOM
|
||||
- Color: blue
|
||||
Silk screen: TOP / BOTTOM
|
||||
- Color: white
|
||||
|
||||
|
||||
# Important sizes
|
||||
|
||||
Clearance: 0.15 mm (6 mils)
|
||||
Track width: 0.15 mm (6 mils)
|
||||
- By design rules: 0.13 mm (5 mils)
|
||||
Drill: 0.25 mm (10 mils)
|
||||
- Vias: 0.25 mm (10 mils) [Design: 0.2 mm (8 mils)]
|
||||
- Pads: 0.6 mm (24 mils)
|
||||
Via: 0.51/0.25 mm (20/10 mils)
|
||||
- By design rules: 0.46/0.2 mm (18/8 mils)
|
||||
- Micro via: no [0.2/0.1 mm (8/4 mils)]
|
||||
- Burried/blind via: no
|
||||
Outer Annular Ring: 0.25 mm (10 mils)
|
||||
- By design rules: 0.25 mm (10 mils)
|
||||
|
||||
Eurocircuits class: 6D
|
||||
|
||||
|
||||
# General stats
|
||||
|
||||
Components count: (SMD/THT)
|
||||
- Top: 61/12 (SMD + THT)
|
||||
- Bottom: 0/0 (NONE)
|
||||
|
||||
Defined tracks:
|
||||
- 0.15 mm (6 mils)
|
||||
- 0.3 mm (12 mils)
|
||||
- 0.64 mm (25 mils)
|
||||
|
||||
Used tracks:
|
||||
- 0.15 mm (6 mils) (276) defined: yes
|
||||
- 0.3 mm (12 mils) (11) defined: yes
|
||||
- 0.64 mm (25 mils) (175) defined: yes
|
||||
|
||||
Defined vias:
|
||||
- 0.51/0.25 mm (20/10 mils)
|
||||
- 0.89/0.51 mm (35/20 mils)
|
||||
|
||||
Used vias:
|
||||
- 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes
|
||||
- 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes
|
||||
|
||||
Holes (excluding vias):
|
||||
- 0.8 mm (31 mils) (4)
|
||||
- 0.85 mm (33 mils) (2)
|
||||
- 0.95 mm (37 mils) (3)
|
||||
- 1.2 mm (47 mils) (20)
|
||||
- 3.2 mm (126 mils) (4)
|
||||
|
|
@ -0,0 +1 @@
|
|||
../5_1_6/light_control-report_simple.txt
|
||||
|
|
@ -991,3 +991,14 @@ def test_qr_lib_1(test_dir):
|
|||
if os.path.isfile(bkp):
|
||||
# Not always there, pcbnew_do can remove it
|
||||
os.remove(bkp)
|
||||
|
||||
|
||||
def test_report_simple_1(test_dir):
|
||||
prj = 'light_control'
|
||||
ctx = context.TestContext(test_dir, 'test_report_simple_1', prj, 'report_simple_1', POS_DIR)
|
||||
ctx.run()
|
||||
ctx.expect_out_file(prj+'-report.txt')
|
||||
ctx.expect_out_file(prj+'-report_simple.txt')
|
||||
ctx.compare_txt(prj+'-report.txt')
|
||||
ctx.compare_txt(prj+'-report_simple.txt')
|
||||
ctx.clean_up()
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
# Example KiBot config file
|
||||
kibot:
|
||||
version: 1
|
||||
|
||||
global:
|
||||
solder_mask_color: blue
|
||||
pcb_finish: ENIG
|
||||
|
||||
outputs:
|
||||
- name: 'report_full'
|
||||
comment: "Full design report"
|
||||
type: report
|
||||
|
||||
- name: 'report_simple'
|
||||
comment: "Simple design report"
|
||||
type: report
|
||||
output_id: _simple
|
||||
options:
|
||||
template: simple
|
||||
|
||||
Loading…
Reference in New Issue