From 28ef08c00a20a55654a13fc850c37fdce432a5e1 Mon Sep 17 00:00:00 2001 From: "Salvador E. Tropea" Date: Thu, 16 Feb 2023 09:16:52 -0300 Subject: [PATCH] [Update XML][KiCad 7] Enabled the board parity check - Needs a patched KiCad, waiting for patch aproval (Bug 13921) --- kibot/pre_update_xml.py | 4 ++-- tests/test_plot/test_preflight.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/kibot/pre_update_xml.py b/kibot/pre_update_xml.py index 14a9c3d5..9e7cc5d5 100644 --- a/kibot/pre_update_xml.py +++ b/kibot/pre_update_xml.py @@ -109,7 +109,7 @@ class Update_XML(BasePreFlight): # noqa: F821 errors.append('PCB net code {} name mismatch ({} vs {})'.format(n, net_name, sch_name)) sch_nodes = net_nodes[n] pcb_nodes = {pad.GetParent().GetReference()+' pin '+pad.GetNumber() - for pad in con.GetNetItems(n, [pcbnew.PCB_PAD_T])} + for pad in con.GetNetItems(n, pcbnew.PCB_PAD_T)} dif = pcb_nodes-sch_nodes if dif: errors.append('PCB net code {} extra connection/s: {}'.format(n, ','.join(list(dif)))) @@ -118,7 +118,7 @@ class Update_XML(BasePreFlight): # noqa: F821 errors.append('PCB net code {} missing connection/s: {}'.format(n, ','.join(list(dif)))) def check_pcb_parity(self): - if GS.ki5 or GS.ki7: + if GS.ki5: logger.error('PCB vs schematic parity only available for KiCad 6') exit(MISSING_TOOL) fname = GS.sch_no_ext+'.xml' diff --git a/tests/test_plot/test_preflight.py b/tests/test_plot/test_preflight.py index 779ce892..f14fb917 100644 --- a/tests/test_plot/test_preflight.py +++ b/tests/test_plot/test_preflight.py @@ -179,7 +179,7 @@ def test_update_xml_1(test_dir): @pytest.mark.slow @pytest.mark.eeschema -@pytest.mark.skipif(context.ki5() or context.ki7(), reason="KiCad 6 implementation") +@pytest.mark.skipif(context.ki5(), reason="KiCad 6 implementation") def test_update_xml_2(test_dir): prj = 'pcb_parity' ctx = context.TestContext(test_dir, prj, 'update_xml_2', '')