diff --git a/CHANGELOG.md b/CHANGELOG.md index 701c5a1a..b382a890 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -35,6 +35,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 when scaling. (#407) - Diff: - Problems when using an output and no variant specified. +- PCB/SCH parity test: + - Workaround for bogus net codes generated by KiCad (#410) ### Changed: - Some R, L and C values that were rejected are accepted now. You just get a diff --git a/kibot/pre_update_xml.py b/kibot/pre_update_xml.py index 4cb052f3..3e57c363 100644 --- a/kibot/pre_update_xml.py +++ b/kibot/pre_update_xml.py @@ -86,36 +86,39 @@ class Update_XML(BasePreFlight): # noqa: F821 for ref in set(comps.keys()).difference(found_comps): errors.append('{} found in schematic, but not in PCB'.format(ref)) - def check_nets(self, net_names, net_nodes, errors): + def check_nets(self, net_nodes, errors): # Total count con = GS.board.GetConnectivity() pcb_net_count = con.GetNetCount()-1 # Removing the bogus net 0 - sch_net_count = len(net_names) + sch_net_count = len(net_nodes) if pcb_net_count != sch_net_count: errors.append('Net count mismatch (PCB {} vs schematic {})'.format(pcb_net_count, sch_net_count)) net_info = GS.board.GetNetInfo() # Names and connection + pcb_net_names = set() for n in net_info.NetsByNetcode(): if not n: # Bogus net code 0 continue - if n not in net_names: - errors.append('PCB net code {} not in schematic'.format(n)) - continue net = net_info.GetNetItem(n) net_name = net.GetNetname() - sch_name = net_names[n] - if net_name != sch_name: - errors.append('PCB net code {} name mismatch ({} vs {})'.format(n, net_name, sch_name)) - sch_nodes = net_nodes[n] + if net_name not in net_nodes: + errors.append('Net `{}` not in schematic'.format(net_name)) + continue + pcb_net_names.add(net_name) + sch_nodes = net_nodes[net_name] pcb_nodes = {pad.GetParent().GetReference()+' pin '+pad.GetNumber() for pad in con.GetNetItems(n, pcbnew.PCB_PAD_T)} dif = pcb_nodes-sch_nodes if dif: - errors.append('PCB net code {} extra connection/s: {}'.format(n, ','.join(list(dif)))) + errors.append('Net `{}` extra PCB connection/s: {}'.format(net_name, ','.join(list(dif)))) dif = sch_nodes-pcb_nodes if dif: - errors.append('PCB net code {} missing connection/s: {}'.format(n, ','.join(list(dif)))) + errors.append('Net `{}` missing PCB connection/s: {}'.format(net_name, ','.join(list(dif)))) + # Now check if the schematic added nets + for name in net_nodes.keys(): + if name not in pcb_net_names: + errors.append('Net `{}` not in PCB'.format(name)) def check_pcb_parity(self): if GS.ki5: @@ -145,20 +148,19 @@ class Update_XML(BasePreFlight): # noqa: F821 logger.debugl(2, '- {}: {}'.format(ref, fp)) comps[ref] = fp netlist = root.find('nets') - net_names = {} net_nodes = {} if netlist is not None: for n in netlist.iter('net'): - code = int(n.get('code')) - net_names[code] = n.get('name') - net_nodes[code] = {node.get('ref')+' pin '+node.get('pin') for node in n.iter('node')} + # This is a useless number stored there just to use disk space and confuse people: + # code = int(n.get('code')) + net_nodes[n.get('name')] = {node.get('ref')+' pin '+node.get('pin') for node in n.iter('node')} # Check with the PCB errors = [] load_board() # Check components self.check_components(comps, errors) # Check the nets - self.check_nets(net_names, net_nodes, errors) + self.check_nets(net_nodes, errors) # Report errors if errors: if self.options.as_warnings: diff --git a/tests/board_samples/kicad_6/pcb_parity.kicad_pcb b/tests/board_samples/kicad_6/pcb_parity.kicad_pcb index 56b40a15..fe6f5fed 100644 --- a/tests/board_samples/kicad_6/pcb_parity.kicad_pcb +++ b/tests/board_samples/kicad_6/pcb_parity.kicad_pcb @@ -183,7 +183,7 @@ (pad "1" smd roundrect locked (at -0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (net 2 "Net-(C1-Pad1)") (tstamp 55440b89-8f8a-483a-9b2b-9ccc95708f75)) (pad "2" smd roundrect locked (at 0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) - (net 1 "GND") (tstamp 3d8a4e48-dfd4-4c64-8dd3-885d6a7ed460)) + (net 3 "VCC") (tstamp 3d8a4e48-dfd4-4c64-8dd3-885d6a7ed460)) (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -220,12 +220,14 @@ (gr_line (start 153 76) (end 144 76) (layer "Edge.Cuts") (width 0.05) (tstamp d534140b-6f16-4b83-8893-ef4b026f6ec9)) (gr_line (start 144 84) (end 153 84) (layer "Edge.Cuts") (width 0.05) (tstamp ea655683-6135-4d3f-a322-1186e1a703b2)) - (segment (start 147.2375 78.6) (end 149.7725 78.6) (width 0.25) (layer "F.Cu") (net 1) (tstamp 4ebf58f7-8428-4480-b240-bb7d3c895103)) (segment (start 150.62249 77.57499) (end 151.161973 78.114473) (width 0.25) (layer "F.Cu") (net 2) (tstamp 4ed009e2-b8f5-47d8-ba45-e73cbf2524c2)) (segment (start 145.3625 78.6) (end 145.3625 79.3) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5505e502-12b2-42b0-9e88-71997ebbcbde)) (segment (start 151.161973 78.114473) (end 151.6475 78.6) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5e3899fa-1efc-49c7-bd03-0723e6564f66)) (segment (start 145.3625 78.6) (end 146.38751 77.57499) (width 0.25) (layer "F.Cu") (net 2) (tstamp 88b2a9f5-ec07-44cc-be7d-6243af8d21a7)) (segment (start 145.3625 79.3) (end 145.3625 81.55) (width 0.25) (layer "F.Cu") (net 2) (tstamp a49ce2ce-5d29-415b-a41f-07567cbabb0f)) (segment (start 146.38751 77.57499) (end 150.62249 77.57499) (width 0.25) (layer "F.Cu") (net 2) (tstamp fd90cb38-571b-4f7c-8630-139c123989e3)) + (segment (start 148.18 81.55) (end 149.7725 79.9575) (width 0.25) (layer "F.Cu") (net 3) (tstamp 0a037a7f-2d45-4c85-bd65-2e305244cf41)) + (segment (start 149.7725 79.9575) (end 149.7725 78.6) (width 0.25) (layer "F.Cu") (net 3) (tstamp daa614be-d445-4c2e-bda9-1a0166355db7)) + (segment (start 147.2375 81.55) (end 148.18 81.55) (width 0.25) (layer "F.Cu") (net 3) (tstamp e8cc7f86-2e2e-41c0-a72f-c3447a410832)) ) diff --git a/tests/board_samples/kicad_7/pcb_parity.kicad_pcb b/tests/board_samples/kicad_7/pcb_parity.kicad_pcb index 563ab797..f44254b8 100644 --- a/tests/board_samples/kicad_7/pcb_parity.kicad_pcb +++ b/tests/board_samples/kicad_7/pcb_parity.kicad_pcb @@ -214,7 +214,7 @@ (pad "1" smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) (net 2 "Net-(C1-Pad1)") (tstamp 55440b89-8f8a-483a-9b2b-9ccc95708f75)) (pad "2" smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) - (net 1 "GND") (tstamp 3d8a4e48-dfd4-4c64-8dd3-885d6a7ed460)) + (net 3 "VCC") (tstamp 3d8a4e48-dfd4-4c64-8dd3-885d6a7ed460)) (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step" (offset (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -257,12 +257,14 @@ (gr_line (start 144 84) (end 153 84) (stroke (width 0.05) (type solid)) (layer "Edge.Cuts") (tstamp ea655683-6135-4d3f-a322-1186e1a703b2)) - (segment (start 147.2375 78.6) (end 149.7725 78.6) (width 0.25) (layer "F.Cu") (net 1) (tstamp 4ebf58f7-8428-4480-b240-bb7d3c895103)) (segment (start 150.62249 77.57499) (end 151.161973 78.114473) (width 0.25) (layer "F.Cu") (net 2) (tstamp 4ed009e2-b8f5-47d8-ba45-e73cbf2524c2)) (segment (start 145.3625 78.6) (end 145.3625 79.3) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5505e502-12b2-42b0-9e88-71997ebbcbde)) (segment (start 151.161973 78.114473) (end 151.6475 78.6) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5e3899fa-1efc-49c7-bd03-0723e6564f66)) (segment (start 145.3625 78.6) (end 146.38751 77.57499) (width 0.25) (layer "F.Cu") (net 2) (tstamp 88b2a9f5-ec07-44cc-be7d-6243af8d21a7)) (segment (start 145.3625 79.3) (end 145.3625 81.55) (width 0.25) (layer "F.Cu") (net 2) (tstamp a49ce2ce-5d29-415b-a41f-07567cbabb0f)) (segment (start 146.38751 77.57499) (end 150.62249 77.57499) (width 0.25) (layer "F.Cu") (net 2) (tstamp fd90cb38-571b-4f7c-8630-139c123989e3)) + (segment (start 148.18 81.55) (end 149.7725 79.9575) (width 0.25) (layer "F.Cu") (net 3) (tstamp 0a037a7f-2d45-4c85-bd65-2e305244cf41)) + (segment (start 149.7725 79.9575) (end 149.7725 78.6) (width 0.25) (layer "F.Cu") (net 3) (tstamp daa614be-d445-4c2e-bda9-1a0166355db7)) + (segment (start 147.2375 81.55) (end 148.18 81.55) (width 0.25) (layer "F.Cu") (net 3) (tstamp e8cc7f86-2e2e-41c0-a72f-c3447a410832)) ) diff --git a/tests/test_plot/test_preflight.py b/tests/test_plot/test_preflight.py index b34d5f55..79094521 100644 --- a/tests/test_plot/test_preflight.py +++ b/tests/test_plot/test_preflight.py @@ -192,7 +192,7 @@ def test_update_xml_1(test_dir): @pytest.mark.slow @pytest.mark.eeschema -@pytest.mark.skipif(context.ki5(), reason="KiCad 6 implementation") +@pytest.mark.skipif(context.ki5(), reason="KiCad 6+ implementation") def test_update_xml_2(test_dir): prj = 'pcb_parity' ctx = context.TestContext(test_dir, prj, 'update_xml_2', '') @@ -208,8 +208,9 @@ def test_update_xml_2(test_dir): "F1 found in PCB, but not in schematic", "FID1 found in schematic, but not in PCB", "Net count mismatch .PCB 3 vs schematic 4.", - "PCB net code 2 name mismatch", - "PCB net code 2 extra connection/s: C1 pin 1"]) + "Net .Net-.C1-Pad1.. not in schematic", + "Net .Net-.R1-Pad2.. not in PCB", + "Net .VCC. extra PCB connection/s: R2 pin 2"]) ctx.clean_up()