diff --git a/CHANGELOG.md b/CHANGELOG.md
index 6e5f23af..a69e62a9 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -63,6 +63,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Fixed
 - The `sketch_plot` option is now implemented.
 - 'ignore_unconnected' preflight wasn't working.
+- The report of hwo many ERC/DRC errors we found.
 
 ## [0.4.0] - 2020-06-17
 ### Added
diff --git a/kiplot/pre_drc.py b/kiplot/pre_drc.py
index de741a37..56aed63e 100644
--- a/kiplot/pre_drc.py
+++ b/kiplot/pre_drc.py
@@ -36,8 +36,10 @@ class Run_DRC(BasePreFlight):  # noqa: F821
         logger.debug('Executing: '+str(cmd))
         ret = call(cmd)
         if ret:
+            if ret > 127:
+                ret = -(256-ret)
             if ret < 0:
                 logger.error('DRC errors: %d', -ret)
             else:
-                logger.error('DRC returned %d', ret)
+                logger.error('DRC returned %d', ret)  # pragma: no cover
             exit(DRC_ERROR)
diff --git a/kiplot/pre_erc.py b/kiplot/pre_erc.py
index 2a078ce5..73dacc26 100644
--- a/kiplot/pre_erc.py
+++ b/kiplot/pre_erc.py
@@ -34,8 +34,10 @@ class Run_ERC(BasePreFlight):  # noqa: F821
         logger.debug('Executing: '+str(cmd))
         ret = call(cmd)
         if ret:
+            if ret > 127:
+                ret = -(256-ret)
             if ret < 0:
                 logger.error('ERC errors: %d', -ret)
             else:
-                logger.error('ERC returned %d', ret)
+                logger.error('ERC returned %d', ret)  # pragma: no cover
             exit(ERC_ERROR)
diff --git a/tests/board_samples/fail-erc.kicad_pcb b/tests/board_samples/fail-erc.kicad_pcb
new file mode 100644
index 00000000..e69de29b
diff --git a/tests/board_samples/fail-erc.sch b/tests/board_samples/fail-erc.sch
new file mode 100644
index 00000000..f758d44e
--- /dev/null
+++ b/tests/board_samples/fail-erc.sch
@@ -0,0 +1,32 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 3
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Sheet
+S 3220 2140 1130 1460
+U 5CA71704
+F0 "Power" 50
+F1 "power.sch" 50
+F2 "VCC" O R 4350 2490 50 
+$EndSheet
+$Sheet
+S 5460 2180 1230 1430
+U 5CA75BC1
+F0 "logic" 50
+F1 "logic.sch" 50
+F2 "VCC" I L 5460 2490 50 
+$EndSheet
+Wire Wire Line
+	4350 2490 5460 2490
+$EndSCHEMATC
diff --git a/tests/board_samples/logic.sch b/tests/board_samples/logic.sch
new file mode 100644
index 00000000..b0d01b40
--- /dev/null
+++ b/tests/board_samples/logic.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 3 3
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L fail-project-rescue:R-passive R1
+U 1 1 5CA75C86
+P 5500 2790
+F 0 "R1" H 5492 2948 40  0000 C CNN
+F 1 "R" H 5492 2872 40  0000 C CNN
+F 2 "Resistor_SMD:R_0402_1005Metric" H 5500 2790 60  0001 C CNN
+F 3 "" H 5500 2790 60  0000 C CNN
+	1    5500 2790
+	1    0    0    -1  
+$EndComp
+$Comp
+L fail-project-rescue:C-passive C2
+U 1 1 5CA76352
+P 5700 2860
+F 0 "C2" V 5654 2904 40  0000 L CNN
+F 1 "C" V 5730 2904 40  0000 L CNN
+F 2 "Capacitor_SMD:C_0402_1005Metric" H 5700 2860 60  0001 C CNN
+F 3 "" H 5700 2860 60  0000 C CNN
+	1    5700 2860
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	5550 2790 5700 2790
+Wire Wire Line
+	5700 2790 5700 2810
+Wire Wire Line
+	5700 2910 5700 3000
+$Comp
+L power:GND #PWR03
+U 1 1 5CA77789
+P 5700 3000
+F 0 "#PWR03" H 5700 2750 50  0001 C CNN
+F 1 "GND" H 5705 2827 50  0000 C CNN
+F 2 "" H 5700 3000 50  0000 C CNN
+F 3 "" H 5700 3000 50  0000 C CNN
+	1    5700 3000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5450 2790 5310 2790
+Text HLabel 5310 2790 0    50   Input ~ 0
+VCC
+$Comp
+L fail-project-rescue:CP-passive C3
+U 1 1 5CA7214E
+P 6110 2580
+F 0 "C3" V 6064 2638 40  0000 L CNN
+F 1 "CP" V 6140 2638 40  0000 L CNN
+F 2 "Capacitor_SMD:CP_Elec_3x5.3" V 6178 2638 60  0001 L CNN
+F 3 "" H 6110 2580 60  0000 C CNN
+	1    6110 2580
+	0    1    1    0   
+$EndComp
+$Comp
+L fail-project-rescue:CP-passive C4
+U 1 1 5CA735B9
+P 6320 2580
+F 0 "C4" V 6274 2638 40  0000 L CNN
+F 1 "CP" V 6350 2638 40  0000 L CNN
+F 2 "Capacitor_SMD:CP_Elec_3x5.3" V 6388 2638 60  0001 L CNN
+F 3 "" H 6320 2580 60  0000 C CNN
+	1    6320 2580
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	6110 2530 6110 2440
+Wire Wire Line
+	6110 2440 6320 2440
+Wire Wire Line
+	6320 2440 6320 2530
+Wire Wire Line
+	6320 2630 6320 2720
+Wire Wire Line
+	6320 2720 6110 2720
+Wire Wire Line
+	6110 2720 6110 2630
+Text Notes 6150 3550 0    50   ~ 0
+Output to Output: ERC error
+$Comp
+L 74xx:74LS04 U1
+U 1 1 5EAD683A
+P 6350 3250
+F 0 "U1" H 6350 3567 50  0000 C CNN
+F 1 "74LS04" H 6350 3476 50  0000 C CNN
+F 2 "" H 6350 3250 50  0001 C CNN
+F 3 "http://www.ti.com/lit/gpn/sn74LS04" H 6350 3250 50  0001 C CNN
+	1    6350 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74xx:74LS04 U1
+U 2 1 5EAD766B
+P 7050 3250
+F 0 "U1" H 7050 2933 50  0000 C CNN
+F 1 "74LS04" H 7050 3024 50  0000 C CNN
+F 2 "" H 7050 3250 50  0001 C CNN
+F 3 "http://www.ti.com/lit/gpn/sn74LS04" H 7050 3250 50  0001 C CNN
+	2    7050 3250
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	6650 3250 6750 3250
+Wire Wire Line
+	6050 3250 6000 3250
+Wire Wire Line
+	6000 3250 6000 3350
+Wire Wire Line
+	7350 3250 7400 3250
+Wire Wire Line
+	7400 3250 7400 3350
+$Comp
+L power:GND #PWR05
+U 1 1 5EAD892D
+P 7400 3350
+F 0 "#PWR05" H 7400 3100 50  0001 C CNN
+F 1 "GND" H 7405 3177 50  0000 C CNN
+F 2 "" H 7400 3350 50  0001 C CNN
+F 3 "" H 7400 3350 50  0001 C CNN
+	1    7400 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR04
+U 1 1 5EAD967D
+P 6000 3350
+F 0 "#PWR04" H 6000 3100 50  0001 C CNN
+F 1 "GND" H 6005 3177 50  0000 C CNN
+F 2 "" H 6000 3350 50  0001 C CNN
+F 3 "" H 6000 3350 50  0001 C CNN
+	1    6000 3350
+	1    0    0    -1  
+$EndComp
+Text Notes 5800 2400 0    50   ~ 0
+No driver ERC warning
+$EndSCHEMATC
diff --git a/tests/board_samples/power.sch b/tests/board_samples/power.sch
new file mode 100644
index 00000000..443b189e
--- /dev/null
+++ b/tests/board_samples/power.sch
@@ -0,0 +1,101 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 2 3
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L fail-project-rescue:CONN_01X02-conn P1
+U 1 1 5CA714F2
+P 4350 3610
+AR Path="/5CA714F2" Ref="P1"  Part="1" 
+AR Path="/5CA71704/5CA714F2" Ref="P1"  Part="1" 
+F 0 "P1" H 4267 3335 50  0000 C CNN
+F 1 "CONN_01X02" H 4267 3426 50  0000 C CNN
+F 2 "Connector_JST:JST_JWPF_B02B-JWPF-SK-R_1x02_P2.00mm_Vertical" H 4350 3610 50  0001 C CNN
+F 3 "" H 4350 3610 50  0000 C CNN
+	1    4350 3610
+	-1   0    0    1   
+$EndComp
+$Comp
+L power:PWR_FLAG #FLG01
+U 1 1 5CA71C3C
+P 4850 3560
+F 0 "#FLG01" H 4850 3655 50  0001 C CNN
+F 1 "PWR_FLAG" H 4850 3783 50  0000 C CNN
+F 2 "" H 4850 3560 50  0000 C CNN
+F 3 "" H 4850 3560 50  0000 C CNN
+	1    4850 3560
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4550 3560 4850 3560
+Connection ~ 4850 3560
+$Comp
+L power:PWR_FLAG #FLG02
+U 1 1 5CA72902
+P 4850 3660
+F 0 "#FLG02" H 4850 3755 50  0001 C CNN
+F 1 "PWR_FLAG" H 4850 3883 50  0000 C CNN
+F 2 "" H 4850 3660 50  0000 C CNN
+F 3 "" H 4850 3660 50  0000 C CNN
+	1    4850 3660
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4550 3660 4850 3660
+Wire Wire Line
+	4850 3660 5210 3660
+Wire Wire Line
+	5210 3660 5210 3760
+Connection ~ 4850 3660
+$Comp
+L power:GND #PWR01
+U 1 1 5CA73F58
+P 5210 3760
+F 0 "#PWR01" H 5210 3510 50  0001 C CNN
+F 1 "GND" H 5215 3587 50  0000 C CNN
+F 2 "" H 5210 3760 50  0000 C CNN
+F 3 "" H 5210 3760 50  0000 C CNN
+	1    5210 3760
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4850 3560 5450 3560
+$Comp
+L fail-project-rescue:C-passive C1
+U 1 1 5CA745A6
+P 5450 3610
+F 0 "C1" V 5404 3654 40  0000 L CNN
+F 1 "C" V 5480 3654 40  0000 L CNN
+F 2 "Capacitor_SMD:C_0402_1005Metric" H 5450 3610 60  0001 C CNN
+F 3 "" H 5450 3610 60  0000 C CNN
+	1    5450 3610
+	0    1    1    0   
+$EndComp
+Connection ~ 5450 3560
+Wire Wire Line
+	5450 3560 5620 3560
+$Comp
+L power:GND #PWR02
+U 1 1 5CA755F5
+P 5450 3660
+F 0 "#PWR02" H 5450 3410 50  0001 C CNN
+F 1 "GND" H 5455 3487 50  0000 C CNN
+F 2 "" H 5450 3660 50  0000 C CNN
+F 3 "" H 5450 3660 50  0000 C CNN
+	1    5450 3660
+	1    0    0    -1  
+$EndComp
+Text HLabel 5620 3560 2    50   Output ~ 0
+VCC
+$EndSCHEMATC
diff --git a/tests/test_plot/test_preflight.py b/tests/test_plot/test_preflight.py
index d2d9fa17..973f5923 100644
--- a/tests/test_plot/test_preflight.py
+++ b/tests/test_plot/test_preflight.py
@@ -23,7 +23,7 @@ if prev_dir not in sys.path:
     sys.path.insert(0, prev_dir)
 # Utils import
 from utils import context
-from kiplot.misc import (DRC_ERROR)
+from kiplot.misc import (DRC_ERROR, ERC_ERROR)
 
 
 def test_erc():
@@ -35,6 +35,15 @@ def test_erc():
     ctx.clean_up()
 
 
+def test_erc_fail():
+    prj = 'fail-erc'
+    ctx = context.TestContext('ERC', prj, 'erc', '')
+    ctx.run(ERC_ERROR)
+    # Check all outputs are there
+    ctx.expect_out_file(prj+'.erc')
+    ctx.clean_up()
+
+
 def test_drc():
     prj = 'bom'
     ctx = context.TestContext('DRC', prj, 'drc', '')