Added support for edge_connector, castellated_pads and edge_plating
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@ -54,6 +54,15 @@ class Globals(FiltersOptions):
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KiCad 6: you should set this in the Board Setup -> Board Finish -> Copper Finish option.
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Currently known are None, HAL, HASL, HAL SnPb, HAL lead-free, ENIG, ENEPIG, Hard gold, ImAg, Immersion Silver,
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Immersion Ag, ImAu, Immersion Gold, Immersion Au, Immersion Tin, Immersion Nickel, OSP and HT_OSP """
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self.edge_connector = 'no'
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""" [yes,no,bevelled] Has the PCB edge connectors?
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KiCad 6: you should set this in the Board Setup -> Board Finish -> Edge card connectors """
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self.castellated_pads = False
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""" Has the PCB castelletad pads?
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KiCad 6: you should set this in the Board Setup -> Board Finish -> Has castellated pads """
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self.edge_plating = False
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""" Has the PCB a plated board edge?
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KiCad 6: you should set this in the Board Setup -> Board Finish -> Plated board edge """
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self.copper_finish = None
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""" {pcb_finish} """
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self.set_doc('filters', " [list(dict)] KiBot warnings to be ignored ")
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@ -88,15 +97,27 @@ class Globals(FiltersOptions):
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if sp is None:
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return
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logger.debug("- Found stack-up information")
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copper_finish = None
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for e in sp[1:]:
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if isinstance(e, list) and isinstance(e[0], Symbol):
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name = e[0].value()
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value = None
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if len(e) > 1:
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if isinstance(e[1], Symbol):
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value = e[1].value()
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else:
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value = str(e[1])
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if name == 'copper_finish':
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copper_finish = str(e[1])
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logger.debug("- Copper finish: "+copper_finish)
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if copper_finish is not None:
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self.pcb_finish = copper_finish
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self.pcb_finish = value
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logger.debug("- Copper finish: "+self.pcb_finish)
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elif name == 'edge_connector':
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self.edge_connector = value
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logger.debug("- Edge connector: "+self.edge_connector)
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elif name == 'castellated_pads':
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self.castellated_pads = value == 'yes'
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logger.debug("- Castellated pads: "+value)
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elif name == 'edge_plating':
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self.edge_plating = value == 'yes'
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logger.debug("- Edge plating: "+value)
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def config(self, parent):
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if GS.ki6() and GS.pcb_file and os.path.isfile(GS.pcb_file):
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@ -121,6 +142,9 @@ class Globals(FiltersOptions):
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GS.global_silk_screen_color = self.set_global(GS.global_silk_screen_color, self.silk_screen_color,
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'silk_screen_color')
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GS.global_pcb_finish = self.set_global(GS.global_pcb_finish, self.pcb_finish, 'pcb_finish')
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GS.global_edge_connector = self.set_global(GS.global_edge_connector, self.edge_connector, 'edge_connector')
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GS.global_castellated_pads = self.set_global(GS.global_castellated_pads, self.castellated_pads, 'castellated_pads')
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GS.global_edge_plating = self.set_global(GS.global_edge_plating, self.edge_plating, 'edge_plating')
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if not GS.out_dir_in_cmd_line and self.out_dir:
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GS.out_dir = os.path.join(os.getcwd(), self.out_dir)
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set_filters(self.unparsed)
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@ -90,6 +90,9 @@ class GS(object):
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global_solder_mask_color = None
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global_silk_screen_color = None
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global_pcb_finish = None
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global_edge_connector = None
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global_castellated_pads = None
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global_edge_plating = None
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test_boolean = True
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@staticmethod
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@ -89,6 +89,14 @@ def to_smd_tht(smd, tht):
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return "NONE"
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def solve_edge_connector(val):
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if val == 'no':
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return ''
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if val == 'bevelled':
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return 'yes, bevelled'
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return val
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class ReportOptions(BaseOptions):
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def __init__(self):
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with document:
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@ -415,23 +423,44 @@ class ReportOptions(BaseOptions):
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self._track_sizes = board.GetTrackWidthList()
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self._tracks_defined = set(self._track_sizes)
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def eval_conditional(self, line):
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context = {k: getattr(self, k) for k in dir(self) if k[0] != '_'}
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res = None
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text = line[2:].strip()
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logger.debug('- Evaluating `{}`'.format(text))
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try:
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res = eval(text, {}, context)
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except Exception as e:
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raise KiPlotConfigurationError('wrong conditional: `{}`\nPython says: `{}`'.format(text, str(e)))
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logger.debug('- Result `{}`'.format(res))
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return res
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def do_template(self, template_file, output_file):
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text = ''
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logger.debug("Report template: `{}`".format(template_file))
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with open(template_file, "rt") as f:
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skip_next = False
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for line in f:
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if skip_next:
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skip_next = False
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continue
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done = False
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if line[0] == '#' and ':' in line:
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context = line[1:].split(':')[0]
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logger.debug("Report context: `{}`".format(context))
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try:
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# Contexts are members called context_*
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line = getattr(self, 'context_'+context)(line[len(context)+2:])
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if line[0] == '#':
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if line.startswith('#?'):
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skip_next = not self.eval_conditional(line)
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done = True
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except AttributeError:
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pass
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if not done:
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raise KiPlotConfigurationError("Unknown context: `{}`".format(context))
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line = ''
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elif ':' in line:
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context = line[1:].split(':')[0]
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logger.debug("- Report context: `{}`".format(context))
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try:
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# Contexts are members called context_*
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line = getattr(self, 'context_'+context)(line[len(context)+2:])
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done = True
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except AttributeError:
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pass
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if not done:
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raise KiPlotConfigurationError("Unknown context: `{}`".format(context))
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if not done:
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# Just replace using any data member (_* excluded)
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line = self.do_replacements(line, self.__dict__)
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@ -448,6 +477,9 @@ class ReportOptions(BaseOptions):
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self.solder_mask_color = GS.global_solder_mask_color
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self.silk_screen_color = GS.global_silk_screen_color
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self.pcb_finish = GS.global_pcb_finish
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self.edge_connector = solve_edge_connector(GS.global_edge_connector)
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self.castellated_pads = GS.global_castellated_pads
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self.edge_plating = GS.global_edge_plating
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self.collect_data(GS.board)
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self.do_template(self.template, fname)
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@ -11,6 +11,14 @@ Solder mask: ${solder_mask}
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Silk screen: ${silk_screen}
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- Color: ${silk_screen_color}
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#?edge_connector or castellated_pads or edge_plating
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Special features:
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#?edge_connector
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- Edge connector: ${edge_connector}
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#?castellated_pads
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- Castellated pads
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#?edge_plating
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- Edge plating
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# Important sizes
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@ -9,6 +9,14 @@ Minimum drill size: ≥ ${drill_mm} mm (finished metalized hole: ${drill_1_mm} m
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Minimum slot width: ≥ ${slot_mm} mm
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Ring collar: ≥ ${oar_mm} mm
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#?edge_connector or castellated_pads or edge_plating
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Special features:
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#?edge_connector
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- Edge connector: ${edge_connector}
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#?castellated_pads
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- Castellated pads
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#?edge_plating
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- Edge plating
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Materials:
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- ${pcb_material}, ${thickness_mm} mm
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@ -52,7 +52,9 @@
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(layer "B.SilkS" (type "Bottom Silk Screen"))
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(copper_finish "ENIG")
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(dielectric_constraints no)
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(edge_connector bevelled)
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(castellated_pads yes)
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(edge_plating yes)
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)
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(pad_to_mask_clearance 0.051)
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(solder_mask_min_width 0.25)
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@ -11,6 +11,10 @@ Solder mask: TOP / BOTTOM
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Silk screen: TOP / BOTTOM
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- Color: white
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Special features:
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- Edge connector: yes, bevelled
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- Castellated pads
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- Edge plating
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# Important sizes
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