Added support for edge_connector, castellated_pads and edge_plating

This commit is contained in:
Salvador E. Tropea 2022-01-16 19:13:20 -03:00
parent da1da26983
commit 514cc949b6
7 changed files with 96 additions and 15 deletions

View File

@ -54,6 +54,15 @@ class Globals(FiltersOptions):
KiCad 6: you should set this in the Board Setup -> Board Finish -> Copper Finish option.
Currently known are None, HAL, HASL, HAL SnPb, HAL lead-free, ENIG, ENEPIG, Hard gold, ImAg, Immersion Silver,
Immersion Ag, ImAu, Immersion Gold, Immersion Au, Immersion Tin, Immersion Nickel, OSP and HT_OSP """
self.edge_connector = 'no'
""" [yes,no,bevelled] Has the PCB edge connectors?
KiCad 6: you should set this in the Board Setup -> Board Finish -> Edge card connectors """
self.castellated_pads = False
""" Has the PCB castelletad pads?
KiCad 6: you should set this in the Board Setup -> Board Finish -> Has castellated pads """
self.edge_plating = False
""" Has the PCB a plated board edge?
KiCad 6: you should set this in the Board Setup -> Board Finish -> Plated board edge """
self.copper_finish = None
""" {pcb_finish} """
self.set_doc('filters', " [list(dict)] KiBot warnings to be ignored ")
@ -88,15 +97,27 @@ class Globals(FiltersOptions):
if sp is None:
return
logger.debug("- Found stack-up information")
copper_finish = None
for e in sp[1:]:
if isinstance(e, list) and isinstance(e[0], Symbol):
name = e[0].value()
value = None
if len(e) > 1:
if isinstance(e[1], Symbol):
value = e[1].value()
else:
value = str(e[1])
if name == 'copper_finish':
copper_finish = str(e[1])
logger.debug("- Copper finish: "+copper_finish)
if copper_finish is not None:
self.pcb_finish = copper_finish
self.pcb_finish = value
logger.debug("- Copper finish: "+self.pcb_finish)
elif name == 'edge_connector':
self.edge_connector = value
logger.debug("- Edge connector: "+self.edge_connector)
elif name == 'castellated_pads':
self.castellated_pads = value == 'yes'
logger.debug("- Castellated pads: "+value)
elif name == 'edge_plating':
self.edge_plating = value == 'yes'
logger.debug("- Edge plating: "+value)
def config(self, parent):
if GS.ki6() and GS.pcb_file and os.path.isfile(GS.pcb_file):
@ -121,6 +142,9 @@ class Globals(FiltersOptions):
GS.global_silk_screen_color = self.set_global(GS.global_silk_screen_color, self.silk_screen_color,
'silk_screen_color')
GS.global_pcb_finish = self.set_global(GS.global_pcb_finish, self.pcb_finish, 'pcb_finish')
GS.global_edge_connector = self.set_global(GS.global_edge_connector, self.edge_connector, 'edge_connector')
GS.global_castellated_pads = self.set_global(GS.global_castellated_pads, self.castellated_pads, 'castellated_pads')
GS.global_edge_plating = self.set_global(GS.global_edge_plating, self.edge_plating, 'edge_plating')
if not GS.out_dir_in_cmd_line and self.out_dir:
GS.out_dir = os.path.join(os.getcwd(), self.out_dir)
set_filters(self.unparsed)

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@ -90,6 +90,9 @@ class GS(object):
global_solder_mask_color = None
global_silk_screen_color = None
global_pcb_finish = None
global_edge_connector = None
global_castellated_pads = None
global_edge_plating = None
test_boolean = True
@staticmethod

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@ -89,6 +89,14 @@ def to_smd_tht(smd, tht):
return "NONE"
def solve_edge_connector(val):
if val == 'no':
return ''
if val == 'bevelled':
return 'yes, bevelled'
return val
class ReportOptions(BaseOptions):
def __init__(self):
with document:
@ -415,23 +423,44 @@ class ReportOptions(BaseOptions):
self._track_sizes = board.GetTrackWidthList()
self._tracks_defined = set(self._track_sizes)
def eval_conditional(self, line):
context = {k: getattr(self, k) for k in dir(self) if k[0] != '_'}
res = None
text = line[2:].strip()
logger.debug('- Evaluating `{}`'.format(text))
try:
res = eval(text, {}, context)
except Exception as e:
raise KiPlotConfigurationError('wrong conditional: `{}`\nPython says: `{}`'.format(text, str(e)))
logger.debug('- Result `{}`'.format(res))
return res
def do_template(self, template_file, output_file):
text = ''
logger.debug("Report template: `{}`".format(template_file))
with open(template_file, "rt") as f:
skip_next = False
for line in f:
if skip_next:
skip_next = False
continue
done = False
if line[0] == '#' and ':' in line:
context = line[1:].split(':')[0]
logger.debug("Report context: `{}`".format(context))
try:
# Contexts are members called context_*
line = getattr(self, 'context_'+context)(line[len(context)+2:])
if line[0] == '#':
if line.startswith('#?'):
skip_next = not self.eval_conditional(line)
done = True
except AttributeError:
pass
if not done:
raise KiPlotConfigurationError("Unknown context: `{}`".format(context))
line = ''
elif ':' in line:
context = line[1:].split(':')[0]
logger.debug("- Report context: `{}`".format(context))
try:
# Contexts are members called context_*
line = getattr(self, 'context_'+context)(line[len(context)+2:])
done = True
except AttributeError:
pass
if not done:
raise KiPlotConfigurationError("Unknown context: `{}`".format(context))
if not done:
# Just replace using any data member (_* excluded)
line = self.do_replacements(line, self.__dict__)
@ -448,6 +477,9 @@ class ReportOptions(BaseOptions):
self.solder_mask_color = GS.global_solder_mask_color
self.silk_screen_color = GS.global_silk_screen_color
self.pcb_finish = GS.global_pcb_finish
self.edge_connector = solve_edge_connector(GS.global_edge_connector)
self.castellated_pads = GS.global_castellated_pads
self.edge_plating = GS.global_edge_plating
self.collect_data(GS.board)
self.do_template(self.template, fname)

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@ -11,6 +11,14 @@ Solder mask: ${solder_mask}
Silk screen: ${silk_screen}
- Color: ${silk_screen_color}
#?edge_connector or castellated_pads or edge_plating
Special features:
#?edge_connector
- Edge connector: ${edge_connector}
#?castellated_pads
- Castellated pads
#?edge_plating
- Edge plating
# Important sizes

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@ -9,6 +9,14 @@ Minimum drill size: ≥ ${drill_mm} mm (finished metalized hole: ${drill_1_mm} m
Minimum slot width: ≥ ${slot_mm} mm
Ring collar: ≥ ${oar_mm} mm
#?edge_connector or castellated_pads or edge_plating
Special features:
#?edge_connector
- Edge connector: ${edge_connector}
#?castellated_pads
- Castellated pads
#?edge_plating
- Edge plating
Materials:
- ${pcb_material}, ${thickness_mm} mm

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@ -52,7 +52,9 @@
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "ENIG")
(dielectric_constraints no)
(edge_connector bevelled)
(castellated_pads yes)
(edge_plating yes)
)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)

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@ -11,6 +11,10 @@ Solder mask: TOP / BOTTOM
Silk screen: TOP / BOTTOM
- Color: white
Special features:
- Edge connector: yes, bevelled
- Castellated pads
- Edge plating
# Important sizes