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[Update_XML] Now you can check PCB and schematic parity 

Related to #297
This commit is contained in:
Salvador E. Tropea 2022-09-21 11:33:26 -03:00
parent 6eaa09beea
commit 58b7958899
10 changed files with 936 additions and 12 deletions
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2
CHANGELOG.md
View File

@ -42,6 +42,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Render_3D: Options to disable some technical layers and control the
silkscreen clipping. (#282)
- Internal BoM: Now you can aggregate components using CSV files. (See #248)
- Now you can check PCB and schematic parity using the `update_xml` preflight
(See #297)
### Fixed
- Problems to compress netlists. (#287)

11
README.md
View File

@ -398,6 +398,8 @@ This section is used to specify tasks that will be executed before generating an
- `text`: [string=''] Text to insert instead of the tag.
- `run_drc`: [boolean=false] Runs the DRC (Distance Rules Check). To ensure we have a valid PCB.
The report file name is controlled by the global output pattern (%i=drc %x=txt).
Note that the KiCad 6 *Test for parity between PCB and schematic* option is not supported.
If you need to check the parity use the `update_xml` preflight.
- `run_erc`: [boolean=false] Runs the ERC (Electrical Rules Check). To ensure the schematic is electrically correct.
The report file name is controlled by the global output pattern (%i=erc %x=txt).
- `sch_replace`: [dict] Replaces tags in the schematic. I.e. to insert the git hash or last revision date.
@ -437,9 +439,16 @@ This section is used to specify tasks that will be executed before generating an
- `update_qr`: [boolean=false] Update the QR codes.
Complements the `qr_lib` output.
The KiCad 6 files and the KiCad 5 PCB needs manual update, generating a new library isn't enough.
- `update_xml`: [boolean=false] Update the XML version of the BoM (Bill of Materials).
- `update_xml`: [boolean=false|dict] Update the XML version of the BoM (Bill of Materials).
To ensure our generated BoM is up to date.
Note that this isn't needed when using the internal BoM generator (`bom`).
You can compare the PCB and schematic netlists using it.
* Valid keys:
- **`check_pcb_parity`**: [boolean=false] Check if the PCB and Schematic are synchronized.
This is equivalent to the *Test for parity between PCB and schematic* of the DRC dialog.
Only available for KiCad 6.
- `as_warnings`: [boolean=false] Inform the problems as warnings and don't stop.
- `enabled`: [boolean=true] Enable the update. This is the replacement for the boolean value.
Here is an example of a *preflight* section:

5
docs/samples/generic_plot.kibot.yaml
View File

@ -53,6 +53,8 @@ preflight:
after: '>'
# [boolean=false] Runs the DRC (Distance Rules Check). To ensure we have a valid PCB.
# The report file name is controlled by the global output pattern (%i=drc %x=txt).
# Note that the KiCad 6 *Test for parity between PCB and schematic* option is not supported.
# If you need to check the parity use the `update_xml` preflight.
run_drc: true
# [boolean=false] Runs the ERC (Electrical Rules Check). To ensure the schematic is electrically correct.
# The report file name is controlled by the global output pattern (%i=erc %x=txt).
@ -80,9 +82,10 @@ preflight:
# Complements the `qr_lib` output.
# The KiCad 6 files and the KiCad 5 PCB needs manual update, generating a new library isn't enough.
update_qr: true
# [boolean=false] Update the XML version of the BoM (Bill of Materials).
# [boolean=false|dict] Update the XML version of the BoM (Bill of Materials).
# To ensure our generated BoM is up to date.
# Note that this isn't needed when using the internal BoM generator (`bom`).
# You can compare the PCB and schematic netlists using it.
update_xml: true
outputs:

3
kibot/misc.py
View File

@ -40,6 +40,7 @@ KICOST_ERROR = 26
MISSING_WKS = 27
MISSING_FILES = 28
DIFF_TOO_BIG = 29
NETLIST_DIFF = 30
error_level_to_name = ['NONE',
'INTERNAL_ERROR',
'WRONG_ARGUMENTS',
@ -70,6 +71,7 @@ error_level_to_name = ['NONE',
'MISSING_WKS',
'MISSING_FILES',
'DIFF_TOO_BIG',
'NETLIST_DIFF',
]
KICOST_SUBMODULE = '../submodules/KiCost/src/kicost'
EXAMPLE_CFG = 'example_template.kibot.yaml'
@ -233,6 +235,7 @@ W_3DRESVER = '(W097) '
W_DOWN3D = '(W098) '
W_MISSREF = '(W099) '
W_COPYOVER = '(W100) '
W_PARITY = '(W101) '
# Somehow arbitrary, the colors are real, but can be different
PCB_MAT_COLORS = {'fr1': "937042", 'fr2': "949d70", 'fr3': "adacb4", 'fr4': "332B16", 'fr5': "6cc290"}
PCB_FINISH_COLORS = {'hal': "8b898c", 'hasl': "8b898c", 'imag': "8b898c", 'enig': "cfb96e", 'enepig': "cfb96e",

4
kibot/pre_run_drc.py
View File

@ -25,7 +25,9 @@ logger = get_logger(__name__)
@pre_class
class Run_DRC(BasePreFlight): # noqa: F821
""" [boolean=false] Runs the DRC (Distance Rules Check). To ensure we have a valid PCB.
The report file name is controlled by the global output pattern (%i=drc %x=txt) """
The report file name is controlled by the global output pattern (%i=drc %x=txt).
Note that the KiCad 6 *Test for parity between PCB and schematic* option is not supported.
If you need to check the parity use the `update_xml` preflight """
def __init__(self, name, value):
super().__init__(name, value)
if not isinstance(value, bool):

143
kibot/pre_update_xml.py
View File

@ -12,32 +12,157 @@ Dependencies:
"""
import os
from sys import exit
from .macros import macros, pre_class # noqa: F401
import xml.etree.ElementTree as ET
from .macros import macros, document, pre_class # noqa: F401
from .error import KiPlotConfigurationError
from .gs import GS
from .kiplot import exec_with_retry, add_extra_options
from .misc import BOM_ERROR
from .kiplot import exec_with_retry, add_extra_options, load_board
from .misc import BOM_ERROR, NETLIST_DIFF, W_PARITY, MISSING_TOOL
from .log import get_logger
from .optionable import Optionable
import pcbnew
logger = get_logger(__name__)
class Update_XMLOptions(Optionable):
""" Reference sorting options """
def __init__(self):
super().__init__()
with document:
self.enabled = True
""" Enable the update. This is the replacement for the boolean value """
self.check_pcb_parity = False
""" *Check if the PCB and Schematic are synchronized.
This is equivalent to the *Test for parity between PCB and schematic* of the DRC dialog.
Only available for KiCad 6 """
self.as_warnings = False
""" Inform the problems as warnings and don't stop """
@pre_class
class Update_XML(BasePreFlight): # noqa: F821
""" [boolean=false] Update the XML version of the BoM (Bill of Materials).
""" [boolean=false|dict] Update the XML version of the BoM (Bill of Materials).
To ensure our generated BoM is up to date.
Note that this isn't needed when using the internal BoM generator (`bom`) """
Note that this isn't needed when using the internal BoM generator (`bom`).
You can compare the PCB and schematic netlists using it """
def __init__(self, name, value):
super().__init__(name, value)
if not isinstance(value, bool):
raise KiPlotConfigurationError('must be boolean')
self._enabled = value
self._check_pcb_parity = False
if isinstance(value, bool):
self._enabled = value
elif isinstance(value, dict):
f = Update_XMLOptions()
f.set_tree(value)
f.config(self)
self._enabled = f.enabled
self._check_pcb_parity = f.check_pcb_parity
self.options = f
self._pcb_related = True
self._sch_related = True
@classmethod
def get_doc(cls):
return cls.__doc__, Update_XMLOptions
def get_targets(self):
""" Returns a list of targets generated by this preflight """
return [GS.sch_no_ext+'.xml']
def check_components(self, comps, errors):
found_comps = set()
for m in GS.get_modules():
ref = m.GetReference()
found_comps.add(ref)
if ref not in comps:
errors.append('{} found in PCB, but not in schematic'.format(ref))
continue
sch_fp = comps[ref]
pcb_fp = m.GetFPIDAsString()
if sch_fp != pcb_fp:
errors.append('{} footprint mismatch (PCB: {} vs schematic: {})'.format(ref, pcb_fp, sch_fp))
for ref in set(comps.keys()).difference(found_comps):
errors.append('{} found in schematic, but not in PCB'.format(ref))
def check_nets(self, net_names, net_nodes, errors):
# Total count
con = GS.board.GetConnectivity()
pcb_net_count = con.GetNetCount()-1 # Removing the bogus net 0
sch_net_count = len(net_names)
if pcb_net_count != sch_net_count:
errors.append('Net count mismatch (PCB {} vs schematic {})'.format(pcb_net_count, sch_net_count))
net_info = GS.board.GetNetInfo()
# Names and connection
for n in net_info.NetsByNetcode():
if not n:
# Bogus net code 0
continue
if n not in net_names:
errors.append('PCB net code {} not in schematic'.format(n))
continue
net = net_info.GetNetItem(n)
net_name = net.GetNetname()
sch_name = net_names[n]
if net_name != sch_name:
errors.append('PCB net code {} name mismatch ({} vs {})'.format(n, net_name, sch_name))
sch_nodes = net_nodes[n]
pcb_nodes = {pad.GetParent().GetReference()+' pin '+pad.GetNumber()
for pad in con.GetNetItems(n, [pcbnew.PCB_PAD_T])}
dif = pcb_nodes-sch_nodes
if dif:
errors.append('PCB net code {} extra connection/s: {}'.format(n, ','.join(list(dif))))
dif = sch_nodes-pcb_nodes
if dif:
errors.append('PCB net code {} missing connection/s: {}'.format(n, ','.join(list(dif))))
def check_pcb_parity(self):
if GS.ki5:
logger.error('PCB vs schematic parity only available for KiCad 6')
exit(MISSING_TOOL)
fname = GS.sch_no_ext+'.xml'
logger.debug('Loading XML: '+fname)
try:
tree = ET.parse(fname)
except Exception as e:
raise KiPlotConfigurationError('Errors parsing {}\n{}'.format(fname, e))
root = tree.getroot()
if root.tag != 'export':
raise KiPlotConfigurationError("{} isn't a valid netlist".format(fname))
# Check version? root.attrib.get('version')
components = root.find('components')
comps = {}
if components is not None:
for c in components.iter('comp'):
ref = c.attrib.get('ref')
fp = c.find('footprint')
fp = fp.text if fp is not None else ''
logger.debugl(2, '- {}: {}'.format(ref, fp))
comps[ref] = fp
netlist = root.find('nets')
net_names = {}
net_nodes = {}
if netlist is not None:
for n in netlist.iter('net'):
code = int(n.get('code'))
net_names[code] = n.get('name')
net_nodes[code] = {node.get('ref')+' pin '+node.get('pin') for node in n.iter('node')}
# Check with the PCB
errors = []
load_board()
# Check components
self.check_components(comps, errors)
# Check the nets
self.check_nets(net_names, net_nodes, errors)
# Report errors
if errors:
if self.options.as_warnings:
for e in errors:
logger.warning(W_PARITY+e)
else:
for e in errors:
logger.error(e)
exit(NETLIST_DIFF)
def run(self):
command = self.ensure_tool('KiAuto')
out_dir = self.expand_dirname(GS.out_dir)
@ -59,3 +184,5 @@ class Update_XML(BasePreFlight): # noqa: F821
video_name = os.path.join(self.expand_dirname(GS.out_dir), 'bom_xml_eeschema_screencast.ogv')
if os.path.isfile(video_name):
os.remove(video_name)
if self._check_pcb_parity:
self.check_pcb_parity()

231
tests/board_samples/kicad_6/pcb_parity.kicad_pcb Normal file
View File

@ -0,0 +1,231 @@
(kicad_pcb (version 20211014) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
)
(setup
(pad_to_mask_clearance 0)
(aux_axis_origin 148.4 80.2)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "GND")
(net 2 "Net-(C1-Pad1)")
(net 3 "VCC")
(footprint "Capacitor_SMD:C_0805_2012Metric" (layer "F.Cu")
(tedit 5B36C52B) (tstamp 00000000-0000-0000-0000-00005ebea01d)
(at 146.3 78.6)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor")
(path "/00000000-0000-0000-0000-00005ebe91ac")
(attr smd)
(fp_text reference "C1" (at 0 -1.65) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp c974f755-f11c-4e72-9337-9b1b03ad46d6)
)
(fp_text value "1uF" (at 0 1.65) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 2b79ad18-d7d7-43df-ab38-e75b2da12556)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 0.5 0.5) (thickness 0.08)))
(tstamp 5db96da7-af8d-43d8-8dc7-a398bfc8659a)
)
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(fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer "F.SilkS") (width 0.12) (tstamp a32b7c78-669e-4058-9e8f-159773d391d1))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp 5298dbf1-ff20-463f-b22f-955b234f027b))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 5ee42af7-ef65-46ec-93e1-21c0e6077de0))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 9aaa51e5-eb42-4e37-9164-e5b31a4cd652))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp e610961e-a821-4b86-8c7d-d4cb27796910))
(fp_line (start -1 0.6) (end -1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 1ffd0374-60f5-4975-8863-7ed9f29dac0e))
(fp_line (start 1 -0.6) (end 1 0.6) (layer "F.Fab") (width 0.1) (tstamp 26a053d6-55aa-4839-adb7-568fd5c066bb))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 8367eaee-e0ca-41eb-bc30-e532a8b59fdd))
(fp_line (start 1 0.6) (end -1 0.6) (layer "F.Fab") (width 0.1) (tstamp e3a76526-d318-4ed9-8120-844abbdc3456))
(pad "1" smd roundrect locked (at -0.9375 0) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 2 "Net-(C1-Pad1)") (tstamp 34fb9d00-02b1-48b3-a790-0112e6a08449))
(pad "2" smd roundrect locked (at 0.9375 0) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 1 "GND") (tstamp 0336c0d4-c4f4-4020-8380-287f839c852a))
(model "${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu")
(tedit 5B36C52B) (tstamp 00000000-0000-0000-0000-00005ebea02e)
(at 146.3 81.55 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor")
(path "/00000000-0000-0000-0000-00005ebe8a2e")
(attr smd)
(fp_text reference "R1" (at 0 -1.65) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
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(effects (font (size 0.5 0.5) (thickness 0.08)))
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(fp_line (start -1 -0.6) (end 1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 337d7915-43e4-4835-8aab-ff527c0de866))
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(pad "1" smd roundrect locked (at -0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 3 "VCC") (tstamp ee158b8c-0101-4c4c-b5ce-76e87c497fb9))
(pad "2" smd roundrect locked (at 0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 2 "Net-(C1-Pad1)") (tstamp b67e7460-96bc-4aa0-8593-880eb3320d89))
(model "${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metrico.step"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu")
(tedit 5B36C52B) (tstamp 00000000-0000-0000-0000-00005ebea03f)
(at 150.71 78.6 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor")
(path "/00000000-0000-0000-0000-00005ebe8e9e")
(attr smd)
(fp_text reference "R2" (at 0 -1.65) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
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(effects (font (size 1 1) (thickness 0.15)))
(tstamp abf3504c-c638-4bb0-8898-7b38d0241a11)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 0.5 0.5) (thickness 0.08)))
(tstamp 730e1bed-bd81-4343-85e9-17d6a47cb046)
)
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tests/board_samples/kicad_6/pcb_parity.kicad_sch Normal file
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(property "Value" "GND" (id 1) (at 114.427 81.8642 0))
(property "Footprint" "" (id 2) (at 114.3 77.47 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "" (id 3) (at 114.3 77.47 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 5d56d28a-c4af-4430-8964-9b60bd37a4ca))
)
(symbol (lib_id "power:PWR_FLAG") (at 114.3 74.93 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-00005ec53a6e)
(property "Reference" "#FLG0101" (id 0) (at 114.3 73.025 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "PWR_FLAG" (id 1) (at 114.3 70.5358 0))
(property "Footprint" "" (id 2) (at 114.3 74.93 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 114.3 74.93 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 3081c45f-0a62-4dc8-a706-c2b3c5e194d8))
)
(symbol (lib_id "power:PWR_FLAG") (at 81.28 49.53 0) (unit 1)
(in_bom yes) (on_board yes)
(uuid 00000000-0000-0000-0000-00005ec53e1a)
(property "Reference" "#FLG0102" (id 0) (at 81.28 47.625 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Value" "PWR_FLAG" (id 1) (at 81.28 45.1358 0))
(property "Footprint" "" (id 2) (at 81.28 49.53 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 81.28 49.53 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 0d525ad4-3f7e-4e8e-b572-5aed774da48c))
)
(symbol (lib_id "Mechanical:Fiducial") (at 114.3 58.42 0) (unit 1)
(in_bom yes) (on_board yes) (fields_autoplaced)
(uuid a356d368-eee7-4981-9ff4-135cb700ad3f)
(property "Reference" "FID1" (id 0) (at 116.84 57.1499 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "Fiducial" (id 1) (at 116.84 59.6899 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "" (id 2) (at 114.3 58.42 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 114.3 58.42 0)
(effects (font (size 1.27 1.27)) hide)
)
)
(sheet_instances
(path "/" (page "1"))
)
(symbol_instances
(path "/00000000-0000-0000-0000-00005ec53a6e"
(reference "#FLG0101") (unit 1) (value "PWR_FLAG") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ec53e1a"
(reference "#FLG0102") (unit 1) (value "PWR_FLAG") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ebe99a0"
(reference "#PWR01") (unit 1) (value "VCC") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ebe9830"
(reference "#PWR02") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ebe965a"
(reference "#PWR03") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ec534bf"
(reference "#PWR0101") (unit 1) (value "GND") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ebe91ac"
(reference "C1") (unit 1) (value "1uF") (footprint "Capacitor_SMD:C_0603_1608Metric")
)
(path "/a356d368-eee7-4981-9ff4-135cb700ad3f"
(reference "FID1") (unit 1) (value "Fiducial") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ebe8a2e"
(reference "R1") (unit 1) (value "100") (footprint "Resistor_SMD:R_0805_2012Metric")
)
(path "/00000000-0000-0000-0000-00005ebe8e9e"
(reference "R2") (unit 1) (value "200") (footprint "Resistor_SMD:R_0805_2012Metric")
)
)
)

25
tests/test_plot/test_preflight.py
View File

@ -20,7 +20,7 @@ import os
import re
from subprocess import run, PIPE
from . import context
from kibot.misc import DRC_ERROR, ERC_ERROR, BOM_ERROR, CORRUPTED_PCB, CORRUPTED_SCH, EXIT_BAD_CONFIG
from kibot.misc import DRC_ERROR, ERC_ERROR, BOM_ERROR, CORRUPTED_PCB, CORRUPTED_SCH, EXIT_BAD_CONFIG, NETLIST_DIFF
@pytest.mark.slow
@ -173,6 +173,29 @@ def test_update_xml_1(test_dir):
ctx.clean_up()
@pytest.mark.slow
@pytest.mark.eeschema
@pytest.mark.skipif(context.ki5(), reason="KiCad 6 implementation")
def test_update_xml_2(test_dir):
prj = 'pcb_parity'
ctx = context.TestContext(test_dir, prj, 'update_xml_2', '')
# The XML should be created where the schematic is located
xml = os.path.abspath(os.path.join(ctx.get_board_dir(), prj+'.xml'))
ctx.run(ret_val=NETLIST_DIFF)
# Check all outputs are there
# ctx.expect_out_file(prj+'.csv')
assert os.path.isfile(xml)
assert os.path.getsize(xml) > 0
logging.debug(os.path.basename(xml)+' OK')
ctx.search_err(["C1 footprint mismatch",
"F1 found in PCB, but not in schematic",
"FID1 found in schematic, but not in PCB",
"Net count mismatch .PCB 3 vs schematic 4.",
"PCB net code 2 name mismatch",
"PCB net code 2 extra connection/s: C1 pin 1"])
ctx.clean_up()
@pytest.mark.slow
@pytest.mark.eeschema
def test_update_xml_fail(test_dir):

9
tests/yaml_samples/update_xml_2.kibot.yaml Normal file
View File

@ -0,0 +1,9 @@
# Example KiBot config file
kibot:
version: 1
preflight:
update_xml:
enabled: true
check_pcb_parity: true
as_warnings: false