[Report] Added warnings and counters for buried and micro vias

- Also added a mechanism to disable them for KiCad 7 which no longer
  provides this option.
This commit is contained in:
Salvador E. Tropea 2023-02-23 08:40:40 -03:00
parent 453d3482fe
commit 659e23ae32
18 changed files with 76 additions and 26 deletions

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@ -5,6 +5,14 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
## [1.6.1] - UNRELEASED
### Added
- Global options:
- allow_blind_buried_vias and allow_microvias for KiCad 7 (no longer in KiCad)
- Report:
- Counters for total vias and by via type (vias_count, thru_vias_count,
blind_vias_count and micro_vias_count)
- Warnings when micro and/or blind vias aren't allowed, but we found them.
### Fixed
- Problems to detect the schematic name when the path to the config contained a
dot that isn't used for an extension and some particular conditions were met.

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@ -741,7 +741,11 @@ global:
- *text*: Alias for value.
- `value`: [string=''] Path to the 3D model.
- *variable*: Alias for name.
- `castellated_pads`: [boolean=false] Has the PCB castelletad pads?
- `allow_blind_buried_vias`: [boolean=true] Allow the use of buried vias. This value is only used for KiCad 7+.
For KiCad 5 and 6 use the design rules settings, stored in the project.
- `allow_microvias`: [boolean=true] Allow the use of micro vias. This value is only used for KiCad 7+.
For KiCad 5 and 6 use the design rules settings, stored in the project.
- `castellated_pads`: [boolean=false] Has the PCB castellated pads?
KiCad 6: you should set this in the Board Setup -> Board Finish -> Has castellated pads.
- *copper_finish*: Alias for pcb_finish.
- `copper_thickness`: [number|string] Copper thickness in micrometers (1 Oz is 35 micrometers).

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@ -1,6 +1,6 @@
# -*- coding: utf-8 -*-
# Copyright (c) 2020-2022 Salvador E. Tropea
# Copyright (c) 2020-2022 Instituto Nacional de Tecnología Industrial
# Copyright (c) 2020-2023 Salvador E. Tropea
# Copyright (c) 2020-2023 Instituto Nacional de Tecnología Industrial
# License: GPL-3.0
# Project: KiBot (formerly KiPlot)
import os
@ -125,7 +125,7 @@ class Globals(FiltersOptions):
The values defined here has precedence over the KiCad configuration.
Related to https://gitlab.com/kicad/code/kicad/-/issues/3792 """
self.castellated_pads = False
""" Has the PCB castelletad pads?
""" Has the PCB castellated pads?
KiCad 6: you should set this in the Board Setup -> Board Finish -> Has castellated pads """
self.copper_finish = None
""" {pcb_finish} """
@ -243,6 +243,12 @@ class Globals(FiltersOptions):
self.field_lcsc_part = ''
""" The name of the schematic field that contains the part number for the LCSC/JLCPCB distributor.
When empty KiBot will try to discover it """
self.allow_blind_buried_vias = True
""" Allow the use of buried vias. This value is only used for KiCad 7+.
For KiCad 5 and 6 use the design rules settings, stored in the project """
self.allow_microvias = True
""" Allow the use of micro vias. This value is only used for KiCad 7+.
For KiCad 5 and 6 use the design rules settings, stored in the project """
self.set_doc('filters', " [list(dict)] KiBot warnings to be ignored ")
self._filter_what = 'KiBot warnings'
self.filters = FilterOptionsKiBot

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@ -163,6 +163,9 @@ class GS(object):
global_units = None
global_use_dir_for_preflights = None
global_variant = None
# Only for v7+
global_allow_blind_buried_vias = None
global_allow_microvias = None
@staticmethod
def set_sch(name):

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@ -100,6 +100,10 @@ MOD_EXCLUDE_FROM_BOM = 8
MOD_BOARD_ONLY = 16 # Footprint has no corresponding symbol
# This is what a virtual component gets when loaded by KiCad 6
MOD_VIRTUAL = MOD_EXCLUDE_FROM_POS_FILES | MOD_EXCLUDE_FROM_BOM
# VIATYPE, not exported by KiCad
VIATYPE_THROUGH = 3
VIATYPE_BLIND_BURIED = 2
VIATYPE_MICROVIA = 1
# Supported values for "do not fit"
DNF = {
@ -253,6 +257,8 @@ W_BADPCB3DTXT = '(W113) '
W_UNKPCB3DNAME = '(W114) '
W_BADPCB3DSTK = '(W115) '
W_EEDA3D = '(W116) '
W_MICROVIAS = '(W117) '
W_BLINDVIAS = '(W118) '
# Somehow arbitrary, the colors are real, but can be different
PCB_MAT_COLORS = {'fr1': "937042", 'fr2': "949d70", 'fr3': "adacb4", 'fr4': "332B16", 'fr5': "6cc290"}
PCB_FINISH_COLORS = {'hal': "8b898c", 'hasl': "8b898c", 'imag': "8b898c", 'enig': "cfb96e", 'enepig': "cfb96e",

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@ -46,7 +46,8 @@ from .kicad.patch_svg import patch_svg_file
from .kicad.config import KiConf
from .kicad.v5_sch import SchError
from .kicad.pcb import PCB
from .misc import PDF_PCB_PRINT, W_PDMASKFAIL, W_MISSTOOL, PCBDRAW_ERR, W_PCBDRAW
from .misc import (PDF_PCB_PRINT, W_PDMASKFAIL, W_MISSTOOL, PCBDRAW_ERR, W_PCBDRAW, VIATYPE_THROUGH, VIATYPE_BLIND_BURIED,
VIATYPE_MICROVIA)
from .create_pdf import create_pdf_from_pages
from .macros import macros, document, output_class # noqa: F401
from .drill_marks import DRILL_MARKS_MAP, add_drill_marks
@ -55,9 +56,6 @@ from . import __version__
from . import log
logger = log.get_logger()
VIATYPE_THROUGH = 3
VIATYPE_BLIND_BURIED = 2
VIATYPE_MICROVIA = 1
POLY_FILL_STYLE = ("fill:{0}; fill-opacity:1.0; stroke:{0}; stroke-width:1; stroke-opacity:1; stroke-linecap:round; "
"stroke-linejoin:round;fill-rule:evenodd;")
DRAWING_LAYERS = ['Dwgs.User', 'Cmts.User', 'Eco1.User', 'Eco2.User']

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@ -22,8 +22,8 @@ import shlex
from subprocess import check_output, STDOUT, CalledProcessError
from .gs import GS
from .misc import (UI_SMD, UI_VIRTUAL, MOD_THROUGH_HOLE, MOD_SMD, MOD_EXCLUDE_FROM_POS_FILES,
FAILED_EXECUTE, W_WRONGEXT, W_WRONGOAR, W_ECCLASST)
from .misc import (UI_SMD, UI_VIRTUAL, MOD_THROUGH_HOLE, MOD_SMD, MOD_EXCLUDE_FROM_POS_FILES, FAILED_EXECUTE, W_WRONGEXT,
W_WRONGOAR, W_ECCLASST, VIATYPE_THROUGH, VIATYPE_BLIND_BURIED, VIATYPE_MICROVIA, W_BLINDVIAS, W_MICROVIAS)
from .registrable import RegOutput
from .out_base import BaseOptions
from .error import KiPlotConfigurationError
@ -39,6 +39,7 @@ INF = float('inf')
EC_SMALL_OAR = GS.from_mm(0.125)
# The minimum drill tool
EC_MIN_DRILL = GS.from_mm(0.1)
YES_NO = ['no', 'yes']
def do_round(v, dig):
@ -306,7 +307,7 @@ class ReportOptions(BaseOptions):
text = ''
for t in sorted(self._tracks_m.keys()):
text += self.do_replacements(line, {'track': t, 'count': self._tracks_m[t],
'defined': 'yes' if t in self._tracks_defined else 'no'})
'defined': YES_NO[t in self._tracks_defined]})
return text
def context_defined_vias(self, line):
@ -336,7 +337,7 @@ class ReportOptions(BaseOptions):
defined['count'] = self._vias[v]
defined['aspect'] = aspect
defined['producibility_level'] = producibility_level
defined['defined'] = 'yes' if (h, d) in self._vias_defined else 'no'
defined['defined'] = YES_NO[(h, d) in self._vias_defined]
text += self.do_replacements(line, defined)
return text
@ -572,6 +573,7 @@ class ReportOptions(BaseOptions):
self._drills_ec = {}
track_type = 'TRACK' if GS.ki5 else 'PCB_TRACK'
via_type = 'VIA' if GS.ki5 else 'PCB_VIA'
self.thru_vias_count = self.blind_vias_count = self.micro_vias_count = self.vias_count = 0
for t in tracks:
tclass = t.GetClass()
if tclass == track_type:
@ -590,6 +592,14 @@ class ReportOptions(BaseOptions):
self.oar_vias_ec = min(self.oar_vias_ec, oar_ec)
self._drills_real[d] = self._drills_real.get(d, 0) + 1
self._drills_ec[d_ec] = self._drills_ec.get(d_ec, 0) + 1
self.vias_count += 1
via_t = via.GetViaType()
if via_t == VIATYPE_THROUGH:
self.thru_vias_count += 1
elif via_t == VIATYPE_BLIND_BURIED:
self.blind_vias_count += 1
elif via_t == VIATYPE_MICROVIA:
self.micro_vias_count += 1
self.track_min = min(self.track_d, self.track)
###########################################################
# Drill (min)
@ -695,11 +705,15 @@ class ReportOptions(BaseOptions):
# Vias
###########################################################
if GS.ki7:
self.micro_vias = 'unknown'
self.blind_vias = 'unknown'
self.micro_vias = YES_NO[GS.global_allow_microvias]
self.blind_vias = YES_NO[GS.global_allow_blind_buried_vias]
else:
self.micro_vias = 'yes' if ds.m_MicroViasAllowed else 'no'
self.blind_vias = 'yes' if ds.m_BlindBuriedViaAllowed else 'no'
self.micro_vias = YES_NO[ds.m_MicroViasAllowed]
self.blind_vias = YES_NO[ds.m_BlindBuriedViaAllowed]
if self.blind_vias == 'no' and self.blind_vias_count:
logger.warning(W_BLINDVIAS+"Buried/blind vias not allowed, but found {}".format(self.blind_vias_count))
if self.micro_vias == 'no' and self.micro_vias_count:
logger.warning(W_MICROVIAS+"Micro vias not allowed, but found {}".format(self.micro_vias_count))
self.uvia_pad = ds.m_MicroViasMinSize
self.uvia_drill = ds.m_MicroViasMinDrill
via_sizes = board.GetViasDimensionsList()

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@ -62,7 +62,8 @@ Via: ${via_pad_mm}/${via_drill_mm} mm (${via_pad_mils}/${via_drill_mils} mils)
- By design rules: ${via_pad_d_mm}/${via_drill_d_mm} mm (${via_pad_d_mils}/${via_drill_d_mils} mils)
- Micro via: ${micro_vias} [${uvia_pad_mm}/${uvia_drill_mm} mm (${uvia_pad_mils}/${uvia_drill_mils} mils)]
- Burried/blind via: ${blind_vias}
- Buried/blind via: ${blind_vias}
- Total: ${vias_count} (thru: ${thru_vias_count} buried/blind: ${blind_vias_count} micro: ${micro_vias_count})
Outer Annular Ring: ${oar_mm} mm (${oar_mils} mils)

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@ -62,7 +62,8 @@ Via: ${via_pad_mm}/${via_drill_mm} mm (${via_pad_mils}/${via_drill_mils} mils)
- By design rules: ${via_pad_d_mm}/${via_drill_d_mm} mm (${via_pad_d_mils}/${via_drill_d_mils} mils)
- Micro via: ${micro_vias} [${uvia_pad_mm}/${uvia_drill_mm} mm (${uvia_pad_mils}/${uvia_drill_mils} mils)]
- Burried/blind via: ${blind_vias}
- Buried/blind via: ${blind_vias}
- Total: ${vias_count} (thru: ${thru_vias_count} buried/blind: ${blind_vias_count} micro: ${micro_vias_count})
Outer Annular Ring: ${oar_mm} mm (${oar_mils} mils)

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@ -0,0 +1 @@
bom.sch

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@ -0,0 +1 @@
bom.kicad_sch

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@ -0,0 +1 @@
bom.kicad_sch

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@ -36,7 +36,8 @@ Via: 0.51/0.25 mm (20/10 mils)
- By design rules: 0.46/0.2 mm (18/8 mils)
- Micro via: no [0.2/0.1 mm (8/4 mils)]
- Burried/blind via: no
- Buried/blind via: no
- Total: 56 (thru: 56 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.08 mm (3 mils)

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@ -36,7 +36,8 @@ Via: 0.51/0.25 mm (20/10 mils)
- By design rules: 0.46/0.2 mm (18/8 mils)
- Micro via: no [0.2/0.1 mm (8/4 mils)]
- Burried/blind via: no
- Buried/blind via: no
- Total: 56 (thru: 56 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.08 mm (3 mils)

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@ -62,7 +62,8 @@ Via: 0.51/0.25 mm (20/10 mils)
- By design rules: 0.46/0.2 mm (18/8 mils)
- Micro via: no [0.2/0.1 mm (8/4 mils)]
- Burried/blind via: no
- Buried/blind via: no
- Total: 56 (thru: 56 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.08 mm (3 mils)

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@ -62,7 +62,8 @@ Via: 0.51/0.25 mm (20/10 mils)
- By design rules: 0.46/0.2 mm (18/8 mils)
- Micro via: no [0.2/0.1 mm (8/4 mils)]
- Burried/blind via: no
- Buried/blind via: no
- Total: 56 (thru: 56 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.08 mm (3 mils)

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@ -61,8 +61,9 @@ Drill: 0.35 mm (14 mils)
Via: 0.51/0.25 mm (20/10 mils)
- By design rules: 0.46/0.2 mm (18/8 mils)
- Micro via: unknown [0.2/0.1 mm (8/4 mils)]
- Burried/blind via: unknown
- Micro via: yes [0.2/0.1 mm (8/4 mils)]
- Buried/blind via: yes
- Total: 56 (thru: 56 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.08 mm (3 mils)

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@ -61,8 +61,9 @@ Drill: 0.35 mm (14 mils)
Via: 0.51/0.25 mm (20/10 mils)
- By design rules: 0.46/0.2 mm (18/8 mils)
- Micro via: unknown [0.2/0.1 mm (8/4 mils)]
- Burried/blind via: unknown
- Micro via: yes [0.2/0.1 mm (8/4 mils)]
- Buried/blind via: yes
- Total: 56 (thru: 56 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.08 mm (3 mils)