Avoid KiAuto warnings about missing project for pdf_pcb_print

This applies to cases using variants.
Now we copy the current project to the temporal location.
Closes #23
This commit is contained in:
Salvador E. Tropea 2020-10-24 16:25:09 -03:00
parent de9628e5c1
commit 68269c10f1
3 changed files with 54 additions and 4 deletions

View File

@ -4,12 +4,13 @@
# License: GPL-3.0
# Project: KiBot (formerly KiPlot)
import os
from shutil import copy2
from tempfile import NamedTemporaryFile
from .pre_base import BasePreFlight
from .error import (KiPlotConfigurationError)
from .gs import (GS)
from .kiplot import check_script, exec_with_retry
from .misc import (CMD_PCBNEW_PRINT_LAYERS, URL_PCBNEW_PRINT_LAYERS, PDF_PCB_PRINT)
from .misc import (CMD_PCBNEW_PRINT_LAYERS, URL_PCBNEW_PRINT_LAYERS, PDF_PCB_PRINT, KICAD_VERSION_5_99)
from .out_base import VariantOptions
from .macros import macros, document, output_class # noqa: F401
from .layer import Layer
@ -56,9 +57,20 @@ class PDF_Pcb_PrintOptions(VariantOptions):
super().config()
self._drill_marks = PDF_Pcb_PrintOptions._drill_marks_map[self._drill_marks]
@staticmethod
def _copy_project(fname):
pro_ext = '.kicad_pro' if GS.kicad_version_n >= KICAD_VERSION_5_99 else '.pro'
pro_name = GS.pcb_file.replace('.kicad_pcb', pro_ext)
if not os.path.isfile(pro_name):
return None
pro_copy = fname.replace('.kicad_pcb', pro_ext)
logger.debug('Copying project `{}` to `{}`'.format(pro_name, pro_copy))
copy2(pro_name, pro_copy)
return pro_copy
def filter_components(self, board):
if not self._comps:
return GS.pcb_file
return GS.pcb_file, None
comps_hash = self.get_refs_hash()
self.cross_modules(board, comps_hash)
self.remove_paste_and_glue(board, comps_hash)
@ -67,9 +79,11 @@ class PDF_Pcb_PrintOptions(VariantOptions):
fname = f.name
logger.debug('Storing filtered PCB to `{}`'.format(fname))
GS.board.Save(fname)
# Copy the project: avoids warnings, could carry some options
fproj = self._copy_project(fname)
self.uncross_modules(board, comps_hash)
self.restore_paste_and_glue(board, comps_hash)
return fname
return fname, fproj
def run(self, output_dir, board, layers):
super().run(board, layers)
@ -90,7 +104,7 @@ class PDF_Pcb_PrintOptions(VariantOptions):
cmd.append('--separate')
if self.mirror:
cmd.append('--mirror')
board_name = self.filter_components(board)
board_name, proj_name = self.filter_components(board)
cmd.extend([board_name, output_dir])
if GS.debug_enabled:
cmd.insert(1, '-vv')
@ -102,6 +116,8 @@ class PDF_Pcb_PrintOptions(VariantOptions):
# Remove the temporal PCB
if board_name != GS.pcb_file:
os.remove(board_name)
if proj_name:
os.remove(proj_name)
if ret: # pragma: no cover
# We check all the arguments, we even load the PCB
# A fail here isn't easy to reproduce

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@ -0,0 +1,33 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

View File

@ -47,6 +47,7 @@ def test_print_variant_1():
ctx.run()
# Check all outputs are there
fname = prj+'-F_Fab.pdf'
ctx.search_err(r'KiCad project file not found', True)
ctx.expect_out_file(fname)
ctx.compare_pdf(fname)
ctx.clean_up()