Avoid KiAuto warnings about missing project for pdf_pcb_print
This applies to cases using variants. Now we copy the current project to the temporal location. Closes #23
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de9628e5c1
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@ -4,12 +4,13 @@
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# License: GPL-3.0
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# License: GPL-3.0
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# Project: KiBot (formerly KiPlot)
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# Project: KiBot (formerly KiPlot)
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import os
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import os
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from shutil import copy2
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from tempfile import NamedTemporaryFile
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from tempfile import NamedTemporaryFile
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from .pre_base import BasePreFlight
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from .pre_base import BasePreFlight
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from .error import (KiPlotConfigurationError)
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from .error import (KiPlotConfigurationError)
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from .gs import (GS)
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from .gs import (GS)
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from .kiplot import check_script, exec_with_retry
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from .kiplot import check_script, exec_with_retry
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from .misc import (CMD_PCBNEW_PRINT_LAYERS, URL_PCBNEW_PRINT_LAYERS, PDF_PCB_PRINT)
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from .misc import (CMD_PCBNEW_PRINT_LAYERS, URL_PCBNEW_PRINT_LAYERS, PDF_PCB_PRINT, KICAD_VERSION_5_99)
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from .out_base import VariantOptions
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from .out_base import VariantOptions
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from .macros import macros, document, output_class # noqa: F401
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from .macros import macros, document, output_class # noqa: F401
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from .layer import Layer
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from .layer import Layer
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@ -56,9 +57,20 @@ class PDF_Pcb_PrintOptions(VariantOptions):
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super().config()
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super().config()
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self._drill_marks = PDF_Pcb_PrintOptions._drill_marks_map[self._drill_marks]
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self._drill_marks = PDF_Pcb_PrintOptions._drill_marks_map[self._drill_marks]
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@staticmethod
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def _copy_project(fname):
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pro_ext = '.kicad_pro' if GS.kicad_version_n >= KICAD_VERSION_5_99 else '.pro'
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pro_name = GS.pcb_file.replace('.kicad_pcb', pro_ext)
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if not os.path.isfile(pro_name):
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return None
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pro_copy = fname.replace('.kicad_pcb', pro_ext)
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logger.debug('Copying project `{}` to `{}`'.format(pro_name, pro_copy))
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copy2(pro_name, pro_copy)
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return pro_copy
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def filter_components(self, board):
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def filter_components(self, board):
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if not self._comps:
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if not self._comps:
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return GS.pcb_file
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return GS.pcb_file, None
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comps_hash = self.get_refs_hash()
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comps_hash = self.get_refs_hash()
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self.cross_modules(board, comps_hash)
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self.cross_modules(board, comps_hash)
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self.remove_paste_and_glue(board, comps_hash)
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self.remove_paste_and_glue(board, comps_hash)
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@ -67,9 +79,11 @@ class PDF_Pcb_PrintOptions(VariantOptions):
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fname = f.name
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fname = f.name
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logger.debug('Storing filtered PCB to `{}`'.format(fname))
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logger.debug('Storing filtered PCB to `{}`'.format(fname))
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GS.board.Save(fname)
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GS.board.Save(fname)
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# Copy the project: avoids warnings, could carry some options
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fproj = self._copy_project(fname)
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self.uncross_modules(board, comps_hash)
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self.uncross_modules(board, comps_hash)
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self.restore_paste_and_glue(board, comps_hash)
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self.restore_paste_and_glue(board, comps_hash)
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return fname
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return fname, fproj
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def run(self, output_dir, board, layers):
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def run(self, output_dir, board, layers):
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super().run(board, layers)
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super().run(board, layers)
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@ -90,7 +104,7 @@ class PDF_Pcb_PrintOptions(VariantOptions):
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cmd.append('--separate')
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cmd.append('--separate')
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if self.mirror:
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if self.mirror:
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cmd.append('--mirror')
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cmd.append('--mirror')
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board_name = self.filter_components(board)
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board_name, proj_name = self.filter_components(board)
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cmd.extend([board_name, output_dir])
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cmd.extend([board_name, output_dir])
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if GS.debug_enabled:
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if GS.debug_enabled:
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cmd.insert(1, '-vv')
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cmd.insert(1, '-vv')
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@ -102,6 +116,8 @@ class PDF_Pcb_PrintOptions(VariantOptions):
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# Remove the temporal PCB
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# Remove the temporal PCB
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if board_name != GS.pcb_file:
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if board_name != GS.pcb_file:
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os.remove(board_name)
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os.remove(board_name)
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if proj_name:
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os.remove(proj_name)
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if ret: # pragma: no cover
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if ret: # pragma: no cover
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# We check all the arguments, we even load the PCB
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# We check all the arguments, we even load the PCB
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# A fail here isn't easy to reproduce
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# A fail here isn't easy to reproduce
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@ -0,0 +1,33 @@
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update=22/05/2015 07:44:53
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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@ -47,6 +47,7 @@ def test_print_variant_1():
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ctx.run()
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ctx.run()
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# Check all outputs are there
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# Check all outputs are there
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fname = prj+'-F_Fab.pdf'
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fname = prj+'-F_Fab.pdf'
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ctx.search_err(r'KiCad project file not found', True)
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ctx.expect_out_file(fname)
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ctx.expect_out_file(fname)
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ctx.compare_pdf(fname)
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ctx.compare_pdf(fname)
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ctx.clean_up()
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ctx.clean_up()
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