[3D Models] Added support for models relative to libs

- New on KiCad v7, but will work for olders
This commit is contained in:
Salvador E. Tropea 2023-02-28 14:00:55 -03:00
parent 6c46b240cf
commit 70d716e561
10 changed files with 1764 additions and 2 deletions

View File

@ -18,7 +18,7 @@ from . import log
logger = log.get_logger()
def do_expand_env(fname, used_extra, extra_debug):
def do_expand_env(fname, used_extra, extra_debug, lib_nickname):
# Is it using ALIAS:xxxxx?
force_used_extra = False
if ':' in fname:
@ -40,6 +40,18 @@ def do_expand_env(fname, used_extra, extra_debug):
if os.path.isfile(full_name_cwd):
full_name = full_name_cwd
force_used_extra = True
else:
# We still missing the 3D model
# Try relative to the footprint lib
aliases = KiConf.get_fp_lib_aliases()
lib_alias = aliases.get(lib_nickname)
if lib_alias is not None:
full_name_lib = os.path.join(lib_alias.uri, fname)
if os.path.isfile(full_name_lib):
logger.debug("- Using path relative to `{}` for `{}` ({})".format(lib_nickname, fname, full_name_lib))
full_name = full_name_lib
# KiCad 5 and 6 will need help
force_used_extra = not GS.ki7
if force_used_extra:
used_extra[0] = True
return full_name
@ -204,6 +216,8 @@ class Base3DOptions(VariantOptions):
# Look for all the footprints
for m in GS.get_modules():
ref = m.GetReference()
lib_id = m.GetFPID()
lib_nickname = str(lib_id.GetLibNickname())
sch_comp = all_comps_hash.get(ref, None)
# Extract the models (the iterator returns copies)
models = m.Models()
@ -221,7 +235,7 @@ class Base3DOptions(VariantOptions):
# Skip filtered footprints
continue
used_extra = [False]
full_name = do_expand_env(m3d.m_Filename, used_extra, extra_debug)
full_name = do_expand_env(m3d.m_Filename, used_extra, extra_debug, lib_nickname)
if not os.path.isfile(full_name):
logger.debugl(2, 'Missing 3D model file {} ({})'.format(full_name, m3d.m_Filename))
# Missing 3D model

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@ -0,0 +1,3 @@
fp-info-cache
*-bak
*-backups

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@ -0,0 +1,3 @@
(fp_lib_table
(lib (name mlib)(type KiCad)(uri ${KIPRJMOD}/my_lib.pretty)(options "")(descr ""))
)

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@ -0,0 +1,36 @@
(footprint "R" (version 20211014) (generator pcbnew)
(layer "F.Cu")
(tedit 5F68FEEE)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
(tags "resistor")
(attr smd)
(fp_text reference "REF**" (at 0 -1.65) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp effead60-2b17-4463-91cf-34792a2b459a)
)
(fp_text value "R_0805_2012Metric" (at 0 1.65) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 83cd9c78-75b4-4eec-9501-2ff4a6e7a26e)
)
(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 0.5 0.5) (thickness 0.08)))
(tstamp b5354c63-16aa-4898-aa0c-eeb3d035fc5f)
)
(fp_line (start -0.227064 -0.735) (end 0.227064 -0.735) (layer "F.SilkS") (width 0.12) (tstamp 1d1dfe66-8d95-48c7-9468-1437fe352fc9))
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(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp 245c0818-3ccc-4969-b35b-0d4f8723400e))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 5b983e02-1ada-4414-ad21-290f1424bf3d))
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(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp f3d9ee21-ffbd-4620-abbf-7bc99e9f4420))
(fp_line (start -1 0.625) (end -1 -0.625) (layer "F.Fab") (width 0.1) (tstamp 37f98079-19ff-4dd9-ac60-76d47722b840))
(fp_line (start 1 0.625) (end -1 0.625) (layer "F.Fab") (width 0.1) (tstamp b0e87530-3bac-4895-be8c-fdb50669192d))
(fp_line (start 1 -0.625) (end 1 0.625) (layer "F.Fab") (width 0.1) (tstamp b1a33891-38ab-48fb-8542-eb6b9260c23c))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer "F.Fab") (width 0.1) (tstamp e73c85cd-37bc-422b-91a3-e268ce9a1281))
(pad "1" smd roundrect (at -0.9125 0) (size 1.025 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.243902) (tstamp 9702d628-9b91-4d58-9130-9271bd872f5b))
(pad "2" smd roundrect (at 0.9125 0) (size 1.025 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.243902) (tstamp 1ad1544b-7ba3-4927-93fd-ab9c0a8dba06))
(model "my_3d/R.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,207 @@
#VRML V2.0 utf8
#kicad StepUp wrl exported
# Copyright (C) 2018, kicad StepUp
#
# This work is licensed under the [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),
# with the following exception:
# To the extent that the creation of electronic designs that use 'Licensed Material' can be considered to be 'Adapted Material',
# then the copyright holder waives article 3 of the license with respect to these designs and any generated files which use data provided
# as part of the 'Licensed Material'.
# You are free to use the library data in your own projects without the obligation to share your project files under this or any other license agreement.
# However, if you wish to redistribute these libraries, or parts thereof (including in modified form) as a collection then the exception above does not apply.
# Please refer to https://github.com/KiCad/kicad-packages3D/blob/master/LICENSE.md for further clarification of the exception.
# Disclaimer of Warranties and Limitation of Liability.
# These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.
# *USE 3D CAD DATA AT YOUR OWN RISK*
# *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.*
#
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View File

@ -0,0 +1,130 @@
(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
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(31 "B.Cu" signal)
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(39 "F.Mask" user)
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(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
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(49 "F.Fab" user)
(50 "User.1" user)
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(57 "User.8" user)
(58 "User.9" user)
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(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref false)
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(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
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(psnegative false)
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(plotreference true)
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(drillshape 1)
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(net 0 "")
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(tstamp 5f46b894-d621-486c-bcf1-0b45db372a95)
(at 135 95)
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(tags "resistor")
(attr smd)
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(effects (font (size 1 1) (thickness 0.15)))
(tstamp 3df8d32e-f609-4b48-9636-ec723e03f868)
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(fp_text value "R_0805_2012Metric" (at 0 1.65) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 61563171-d4b5-4679-894f-78943ce23089)
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(fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
(effects (font (size 0.5 0.5) (thickness 0.08)))
(tstamp be42099a-e595-4180-a3eb-149e19148be3)
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(model "my_3d/R.wrl"
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(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
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)

View File

@ -0,0 +1,77 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"images": 0.6,
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"zones": 0.6
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"footprints": true,
"graphics": true,
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"visible_layers": "fffffff_ffffffff",
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"meta": {
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},
"project": {
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}
}

View File

@ -0,0 +1,229 @@
{
"board": {
"3dviewports": [],
"design_settings": {
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"copper_line_width": 0.19999999999999998,
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"dimension_precision": 4,
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"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
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"solder_mask_to_copper_clearance": 0.0,
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"teardrop_options": [
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{
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},
"layer_presets": [],
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},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "test.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
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"diff_pair_width": 0.2,
"line_style": 0,
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
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"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
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"vrml": ""
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}

View File

@ -123,6 +123,20 @@ def test_step_variant_1(test_dir):
ctx.clean_up(keep_project=True)
@pytest.mark.skipif(not context.ki7(), reason="KiCad 7 3D relative dirs")
def test_step_rel_dir_1(test_dir):
prj = 'test'
ctx = context.TestContext(test_dir, '3d_rel_path/'+prj, 'step_simple', STEP_DIR)
ctx.run()
# Check all outputs are there
name = prj+'-3D.step'
ctx.expect_out_file_d(name)
# Check the R and C 3D models are there
ctx.search_in_file_d(name, [r"PRODUCT\('R',"])
ctx.search_err(['Add component R1'])
ctx.clean_up(keep_project=True)
@pytest.mark.slow
@pytest.mark.pcbnew
def test_render_3d_variant_1(test_dir):