diff --git a/tests/reference/5_1_6/bom-F_Cu+F_SilkS.svg b/tests/reference/5_1_6/bom-F_Cu+F_SilkS.svg
new file mode 100644
index 00000000..702b7661
--- /dev/null
+++ b/tests/reference/5_1_6/bom-F_Cu+F_SilkS.svg
@@ -0,0 +1,39 @@
+
+
diff --git a/tests/reference/5_1_7/bom-F_Cu+F_SilkS.svg b/tests/reference/5_1_7/bom-F_Cu+F_SilkS.svg
new file mode 120000
index 00000000..29f1229e
--- /dev/null
+++ b/tests/reference/5_1_7/bom-F_Cu+F_SilkS.svg
@@ -0,0 +1 @@
+../5_1_6/bom-F_Cu+F_SilkS.svg
\ No newline at end of file
diff --git a/tests/reference/6_0_4/bom-F_Cu+F_SilkS.svg b/tests/reference/6_0_4/bom-F_Cu+F_SilkS.svg
new file mode 100644
index 00000000..1970bb1b
--- /dev/null
+++ b/tests/reference/6_0_4/bom-F_Cu+F_SilkS.svg
@@ -0,0 +1,63 @@
+
+
diff --git a/tests/test_plot/test_print_pcb.py b/tests/test_plot/test_print_pcb.py
index db7b542d..08ca97fc 100644
--- a/tests/test_plot/test_print_pcb.py
+++ b/tests/test_plot/test_print_pcb.py
@@ -33,6 +33,17 @@ def test_print_pcb_simple(test_dir):
ctx.clean_up()
+def test_print_pcb_svg_simple(test_dir):
+ prj = 'bom'
+ ctx = context.TestContext(test_dir, 'print_pcb_svg_simple', prj, 'print_pcb_svg', '')
+ ctx.run()
+ # Check all outputs are there
+ file = PDF_FILE.replace('.pdf', '.svg')
+ ctx.expect_out_file(file)
+ ctx.compare_image(file)
+ ctx.clean_up()
+
+
def test_print_pcb_refill_1(test_dir):
prj = 'zone-refill'
ctx = context.TestContext(test_dir, 'print_pcb_refill', prj, 'print_pcb_zone-refill', '')
diff --git a/tests/yaml_samples/print_pcb_svg.kibot.yaml b/tests/yaml_samples/print_pcb_svg.kibot.yaml
new file mode 100644
index 00000000..08c92823
--- /dev/null
+++ b/tests/yaml_samples/print_pcb_svg.kibot.yaml
@@ -0,0 +1,15 @@
+# Example KiBot config file
+kibot:
+ version: 1
+
+outputs:
+ - name: 'print_front'
+ comment: "Print F.Cu+F.SilkS"
+ type: svg_pcb_print
+ options:
+ title: 'Fake title for front copper and silk'
+ scaling: 12
+ plot_sheet_reference: false
+ layers:
+ - layer: F.Cu
+ - layer: F.SilkS