From 3fc1947fcf6ebff77fc4f41bb850176c92e12eec Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Wed, 17 Jan 2024 12:35:27 +0100 Subject: [PATCH 1/2] pre_update: Honor 'board_only' (Not in schematic) footprint property. It is quite common, to add footprints to a PCB, without adding it to the schematic. Think Logo's or 'duplicate' connectors etc. KiCad has a flag called 'Not in schematic' for this purpose. Lets check if this flag is set in the PCB, and ignore any errors from this if applicable. Fixes: #558. Signed-off-by: Olliver Schinagl --- CHANGELOG.md | 1 + kibot/pre_update_xml.py | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 42070e11..348d0fb9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -130,6 +130,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 This limitation isn't found on KiCad 7. (#486) - *exclude_from_bom* mismatch on KiCad 7 - *Sheetfile* mismatch on KiCad 7 when testing from different directory + - Honor the 'Not in schematic' (board_only) flag when doing a parity check - Dependencies downloader: - Problems when connection timed-out - Sub PCB separation using annotation method for some edeges and KiCad diff --git a/kibot/pre_update_xml.py b/kibot/pre_update_xml.py index 3df64a84..4903276d 100644 --- a/kibot/pre_update_xml.py +++ b/kibot/pre_update_xml.py @@ -86,7 +86,8 @@ class Update_XML(BasePreFlight): # noqa: F821 logger.warning(W_NOTINBOM+f"{ref} excluded from BoM we can't check its parity, upgrade to KiCad 7") excluded.add(ref) else: - errors.append('{} found in PCB, but not in schematic'.format(ref)) + if not m.GetAttributes() & MOD_BOARD_ONLY: + errors.append('{} found in PCB, but not in schematic'.format(ref)) continue sch_data = comps[ref] pcb_fp = m.GetFPIDAsString() From 1475b5894cb9d6865eae57ffec27210b36c41e65 Mon Sep 17 00:00:00 2001 From: "Salvador E. Tropea" Date: Wed, 17 Jan 2024 12:58:05 -0300 Subject: [PATCH 2/2] [Update XML] Fixed missing import and added test case For the "board only" check --- kibot/pre_update_xml.py | 2 +- .../kicad_7/parity_not_in_bom.kicad_pcb | 29 +++++++++++++++++-- .../kicad_8/parity_not_in_bom.kicad_pcb | 29 +++++++++++++++++-- 3 files changed, 53 insertions(+), 7 deletions(-) diff --git a/kibot/pre_update_xml.py b/kibot/pre_update_xml.py index 4903276d..79766917 100644 --- a/kibot/pre_update_xml.py +++ b/kibot/pre_update_xml.py @@ -17,7 +17,7 @@ from .macros import macros, document, pre_class # noqa: F401 from .error import KiPlotConfigurationError from .gs import GS from .kiplot import load_board -from .misc import BOM_ERROR, NETLIST_DIFF, W_PARITY, MISSING_TOOL, KICAD_VERSION_7_0_1, W_NOTINBOM +from .misc import BOM_ERROR, NETLIST_DIFF, W_PARITY, MISSING_TOOL, KICAD_VERSION_7_0_1, W_NOTINBOM, MOD_BOARD_ONLY from .log import get_logger from .optionable import Optionable import pcbnew diff --git a/tests/board_samples/kicad_7/parity_not_in_bom.kicad_pcb b/tests/board_samples/kicad_7/parity_not_in_bom.kicad_pcb index 9f877f06..13daf7d9 100644 --- a/tests/board_samples/kicad_7/parity_not_in_bom.kicad_pcb +++ b/tests/board_samples/kicad_7/parity_not_in_bom.kicad_pcb @@ -75,13 +75,36 @@ ) ) - (property "MYVAR" "tests/data") - (property "PRUEBITA" "Hola!") - (net 0 "") (net 1 "Net-(R1-Pad1)") (net 2 "Net-(R1-Pad2)") + (footprint "Fiducial:Fiducial_0.5mm_Mask1.5mm" (layer "F.Cu") + (tstamp 70f9582f-1ec1-4a67-9f43-9e0435f03ddd) + (at 147.7 87.3) + (descr "Circular Fiducial, 0.5mm bare copper, 1.5mm soldermask opening") + (tags "fiducial") + (attr smd board_only) + (fp_text reference "F1" (at -1.9 -0.3) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e2911034-881c-4775-a5f7-cb8d4b2bfddd) + ) + (fp_text value "Fiducial_0.5mm_Mask1.5mm" (at 12.5 0.1) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 3417dce9-cef6-4e6b-862d-204bab5dd510) + ) + (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab") + (effects (font (size 0.2 0.2) (thickness 0.04))) + (tstamp 210396ae-f0ba-4458-b6f9-96a4a2add864) + ) + (fp_circle (center 0 0) (end 1 0) + (stroke (width 0.05) (type solid)) (fill none) (layer "F.CrtYd") (tstamp 1725cd30-9834-479b-b85d-ebac3c00e855)) + (fp_circle (center 0 0) (end 0.75 0) + (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 3f0dc753-58a8-4bed-973d-a176a44e7f14)) + (pad "" smd circle (at 0 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask") + (solder_mask_margin 0.5) (clearance 0.5) (tstamp c4ff1230-71db-459d-bb50-88f2d096fd24)) + ) + (footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu") (tstamp 71391f61-a293-4f48-90fc-560a7915df90) (at 141.7 90.21) diff --git a/tests/board_samples/kicad_8/parity_not_in_bom.kicad_pcb b/tests/board_samples/kicad_8/parity_not_in_bom.kicad_pcb index 9f877f06..13daf7d9 100644 --- a/tests/board_samples/kicad_8/parity_not_in_bom.kicad_pcb +++ b/tests/board_samples/kicad_8/parity_not_in_bom.kicad_pcb @@ -75,13 +75,36 @@ ) ) - (property "MYVAR" "tests/data") - (property "PRUEBITA" "Hola!") - (net 0 "") (net 1 "Net-(R1-Pad1)") (net 2 "Net-(R1-Pad2)") + (footprint "Fiducial:Fiducial_0.5mm_Mask1.5mm" (layer "F.Cu") + (tstamp 70f9582f-1ec1-4a67-9f43-9e0435f03ddd) + (at 147.7 87.3) + (descr "Circular Fiducial, 0.5mm bare copper, 1.5mm soldermask opening") + (tags "fiducial") + (attr smd board_only) + (fp_text reference "F1" (at -1.9 -0.3) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e2911034-881c-4775-a5f7-cb8d4b2bfddd) + ) + (fp_text value "Fiducial_0.5mm_Mask1.5mm" (at 12.5 0.1) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 3417dce9-cef6-4e6b-862d-204bab5dd510) + ) + (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab") + (effects (font (size 0.2 0.2) (thickness 0.04))) + (tstamp 210396ae-f0ba-4458-b6f9-96a4a2add864) + ) + (fp_circle (center 0 0) (end 1 0) + (stroke (width 0.05) (type solid)) (fill none) (layer "F.CrtYd") (tstamp 1725cd30-9834-479b-b85d-ebac3c00e855)) + (fp_circle (center 0 0) (end 0.75 0) + (stroke (width 0.1) (type solid)) (fill none) (layer "F.Fab") (tstamp 3f0dc753-58a8-4bed-973d-a176a44e7f14)) + (pad "" smd circle (at 0 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask") + (solder_mask_margin 0.5) (clearance 0.5) (tstamp c4ff1230-71db-459d-bb50-88f2d096fd24)) + ) + (footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu") (tstamp 71391f61-a293-4f48-90fc-560a7915df90) (at 141.7 90.21)