diff --git a/CHANGELOG.md b/CHANGELOG.md index 12533311..6e5f23af 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -62,6 +62,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 ### Fixed - The `sketch_plot` option is now implemented. +- 'ignore_unconnected' preflight wasn't working. ## [0.4.0] - 2020-06-17 ### Added diff --git a/kiplot/pre_base.py b/kiplot/pre_base.py index 2730ef59..6d67bef4 100644 --- a/kiplot/pre_base.py +++ b/kiplot/pre_base.py @@ -88,8 +88,8 @@ class BasePreFlight(object): """ Returns a YAML value for the example config """ return 'true' - def run(self, brd_file): # pragma: no cover - logger.error("The run method for the preflight class name `{}` isn't implemented".format(self._name)) + def run(self): + pass - def apply(self, brd_file): # pragma: no cover - logger.error("The apply method for the preflight class name `{}` isn't implemented".format(self._name)) + def apply(self): + pass diff --git a/kiplot/pre_check_zone_fills.py b/kiplot/pre_check_zone_fills.py index 71b0f719..1a161f57 100644 --- a/kiplot/pre_check_zone_fills.py +++ b/kiplot/pre_check_zone_fills.py @@ -11,8 +11,5 @@ class Check_Zone_Fills(BasePreFlight): # noqa: F821 raise KiPlotConfigurationError('must be boolean') self._enabled = value - def run(self): - pass - def apply(self): BasePreFlight._set_option('check_zone_fills', self._enabled) # noqa: F821 diff --git a/kiplot/pre_drc.py b/kiplot/pre_drc.py index 66265f8e..de741a37 100644 --- a/kiplot/pre_drc.py +++ b/kiplot/pre_drc.py @@ -25,13 +25,13 @@ class Run_DRC(BasePreFlight): # noqa: F821 cmd = [CMD_PCBNEW_RUN_DRC, 'run_drc'] if GS.filter_file: cmd.extend(['-f', GS.filter_file]) + if BasePreFlight.get_option('ignore_unconnected'): # noqa: F821 + cmd.append('-i') cmd.extend([GS.pcb_file, GS.out_dir]) # If we are in verbose mode enable debug in the child if GS.debug_enabled: cmd.insert(1, '-vv') cmd.insert(1, '-r') - if BasePreFlight.get_option('ignore_unconnected'): # noqa: F821 - cmd.insert(1, '-i') logger.info('- Running the DRC') logger.debug('Executing: '+str(cmd)) ret = call(cmd) @@ -41,6 +41,3 @@ class Run_DRC(BasePreFlight): # noqa: F821 else: logger.error('DRC returned %d', ret) exit(DRC_ERROR) - - def apply(self): - pass diff --git a/kiplot/pre_erc.py b/kiplot/pre_erc.py index 3a432c1f..2a078ce5 100644 --- a/kiplot/pre_erc.py +++ b/kiplot/pre_erc.py @@ -39,6 +39,3 @@ class Run_ERC(BasePreFlight): # noqa: F821 else: logger.error('ERC returned %d', ret) exit(ERC_ERROR) - - def apply(self): - pass diff --git a/kiplot/pre_filters.py b/kiplot/pre_filters.py index 117e4d2f..f4f47d8a 100644 --- a/kiplot/pre_filters.py +++ b/kiplot/pre_filters.py @@ -13,9 +13,6 @@ class Filters(BasePreFlight): # noqa: F821 """ Returns a YAML value for the example config """ return "\n - filter: 'Filter description'\n number: 10\n regex: 'Regular expression to match'" - def run(self): - pass - def apply(self): # Create the filters file if self._value: diff --git a/kiplot/pre_ignore_unconnected.py b/kiplot/pre_ignore_unconnected.py index 9d783565..ef92fd4d 100644 --- a/kiplot/pre_ignore_unconnected.py +++ b/kiplot/pre_ignore_unconnected.py @@ -15,8 +15,5 @@ class Ignore_Unconnected(BasePreFlight): # noqa: F821 """ Returns a YAML value for the example config """ return 'false' - def run(self, brd_file): - pass - def apply(self): BasePreFlight._set_option('ignore_unconnected', self._enabled) # noqa: F821 diff --git a/kiplot/pre_update_xml.py b/kiplot/pre_update_xml.py index 10c9efbf..b0ac852c 100644 --- a/kiplot/pre_update_xml.py +++ b/kiplot/pre_update_xml.py @@ -33,6 +33,3 @@ class Update_XML(BasePreFlight): # noqa: F821 if ret: logger.error('Failed to update the BoM, error %d', ret) exit(BOM_ERROR) - - def apply(self): - pass diff --git a/tests/board_samples/warning-project.kicad_pcb b/tests/board_samples/warning-project.kicad_pcb new file mode 100644 index 00000000..98d2bcb9 --- /dev/null +++ b/tests/board_samples/warning-project.kicad_pcb @@ -0,0 +1,275 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.0) + + (general + (thickness 1.6) + (drawings 4) + (tracks 10) + (zones 0) + (modules 4) + (nets 4) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.051) + (solder_mask_min_width 0.25) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 "Net-(C2-Pad1)") + (net 3 VCC) + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net GND) + (add_net "Net-(C2-Pad1)") + (add_net VCC) + ) + + (module Capacitor_SMD:C_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5CA72801) + (at 164.775001 80.505001 90) + (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5CA71704/5CA745A6) + (attr smd) + (fp_text reference C1 (at 0 -1.17 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value C (at 0 1.17 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.04))) + ) + (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 VCC)) + (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_0402_1005Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5CA72810) + (at 170.18 80.020001 90) + (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /5CA75BC1/5CA76352) + (attr smd) + (fp_text reference C2 (at 0 -1.17 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value C (at 0 1.17 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.04))) + ) + (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) + (pad 2 smd roundrect (at 0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 1 smd roundrect (at -0.485 0 90) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 "Net-(C2-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_JST:JST_JWPF_B02B-JWPF-SK-R_1x02_P2.00mm_Vertical (layer F.Cu) (tedit 5B772B89) (tstamp 5CA7282D) + (at 154.94 80.01) + (descr "JST JWPF series connector, B02B-JWPF-SK-R (http://www.jst-mfg.com/product/pdf/eng/eJWPF1.pdf), generated with kicad-footprint-generator") + (tags "connector JST JWPF side entry") + (path /5CA71704/5CA714F2) + (fp_text reference P1 (at -1.35 -3.7) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X02 (at -1.35 5.7) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_arc (start 1.7 -1.5) (end 1.7 -2.5) (angle 90) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.7 3.5) (end 2.7 3.5) (angle 90) (layer F.Fab) (width 0.1)) + (fp_arc (start 1.81 -1.61) (end 1.81 -2.61) (angle 90) (layer F.SilkS) (width 0.12)) + (fp_arc (start 1.81 3.61) (end 2.81 3.61) (angle 90) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.9 -3) (end -5.9 5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.9 5) (end 3.2 5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.2 5) (end 3.2 -3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.2 -3) (end -5.9 -3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -2.5) (end -5.4 -2.5) (layer F.Fab) (width 0.1)) + (fp_line (start -5.4 -2.5) (end -5.4 4.5) (layer F.Fab) (width 0.1)) + (fp_line (start -5.4 4.5) (end 1.7 4.5) (layer F.Fab) (width 0.1)) + (fp_line (start 2.7 -1.5) (end 2.7 3.5) (layer F.Fab) (width 0.1)) + (fp_line (start 1.81 -2.61) (end -5.51 -2.61) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.51 -2.61) (end -5.51 4.61) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.51 4.61) (end 1.81 4.61) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.81 -1.61) (end 2.81 3.61) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.75 -1.35) (end -5.75 -2.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.75 -2.85) (end -4.25 -2.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.375 -1.9) (end 0.375 -1.9) (layer F.Fab) (width 0.1)) + (fp_line (start 0.375 -1.9) (end 0 -1.15) (layer F.Fab) (width 0.1)) + (fp_line (start 0 -1.15) (end -0.375 -1.9) (layer F.Fab) (width 0.1)) + (fp_text user %R (at -4.7 1 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole roundrect (at 0 0) (size 2 1.3) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.192308) + (net 1 GND)) + (pad 2 thru_hole oval (at 0 2) (size 2 1.3) (drill 1) (layers *.Cu *.Mask) + (net 3 VCC)) + (pad "" np_thru_hole circle (at -1.5 4.05) (size 1.15 1.15) (drill 1.15) (layers *.Cu *.Mask)) + (model ${KISYS3DMOD}/Connector_JST.3dshapes/JST_JWPF_B02B-JWPF-SK-R_1x02_P2.00mm_Vertical.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistor_SMD:R_0402_1005Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5CA7283C) + (at 167.64 83.82) + (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags resistor) + (path /5CA75BC1/5CA75C86) + (attr smd) + (fp_text reference R1 (at 0 -1.17) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value R (at 0 1.17) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1)) + (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.25 0.25) (thickness 0.04))) + ) + (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 VCC)) + (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 "Net-(C2-Pad1)")) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_line (start 187.96 69.85) (end 142.24 69.85) (layer F.SilkS) (width 0.12)) + (gr_line (start 187.96 91.44) (end 187.96 69.85) (layer F.SilkS) (width 0.12)) + (gr_line (start 142.24 91.44) (end 187.96 91.44) (layer F.SilkS) (width 0.12)) + (gr_line (start 142.24 69.85) (end 142.24 91.44) (layer F.SilkS) (width 0.12)) + + (segment (start 164.765 80.01) (end 164.775001 80.020001) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 154.94 80.01) (end 164.765 80.01) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 170.18 81.765) (end 168.125 83.82) (width 0.25) (layer F.Cu) (net 2)) + (segment (start 170.18 80.505001) (end 170.18 81.765) (width 0.25) (layer F.Cu) (net 2)) + (segment (start 167.155 83.37) (end 165.1 81.315) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 167.155 83.82) (end 167.155 83.37) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 165.1 81.315) (end 164.775001 80.990001) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 164.775001 80.990001) (end 157.769999 80.990001) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 156.75 82.01) (end 154.94 82.01) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 157.769999 80.990001) (end 156.75 82.01) (width 0.25) (layer F.Cu) (net 3)) + +) diff --git a/tests/test_plot/test_preflight.py b/tests/test_plot/test_preflight.py index 12acdd06..c884a464 100644 --- a/tests/test_plot/test_preflight.py +++ b/tests/test_plot/test_preflight.py @@ -50,6 +50,16 @@ def test_drc_filter(): ctx.clean_up() +def test_drc_unco(): + """ Check we can ignore unconnected nets """ + prj = 'warning-project' + ctx = context.TestContext('DRC', prj, 'drc_unco', '') + ctx.run() + # Check all outputs are there + ctx.expect_out_file('drc_result.rpt') + ctx.clean_up() + + def test_update_xml(): prj = 'bom' ctx = context.TestContext('Update_XML', prj, 'update_xml', '') diff --git a/tests/test_plot/test_yaml_errors.py b/tests/test_plot/test_yaml_errors.py index 32e91dac..c9de1d5a 100644 --- a/tests/test_plot/test_yaml_errors.py +++ b/tests/test_plot/test_yaml_errors.py @@ -320,12 +320,21 @@ def test_error_pre_unk(): def test_error_wrong_type_1(): + """ run_drc = number """ ctx = context.TestContext('ErrorWrongType1', PRJ, 'error_pre_wrong_type_1', '') ctx.run(EXIT_BAD_CONFIG) assert ctx.search_err("In preflight 'run_drc': must be boolean") ctx.clean_up() +def test_error_wrong_type_2(): + """ ignore_unconnected = string """ + ctx = context.TestContext('ErrorWrongType2', PRJ, 'error_pre_wrong_type_2', '') + ctx.run(EXIT_BAD_CONFIG) + assert ctx.search_err("In preflight 'ignore_unconnected': must be boolean") + ctx.clean_up() + + def test_error_yaml(): ctx = context.TestContext('ErrorYAML', PRJ, 'error_yaml', '') ctx.run(EXIT_BAD_CONFIG) diff --git a/tests/yaml_samples/drc_unco.kiplot.yaml b/tests/yaml_samples/drc_unco.kiplot.yaml new file mode 100644 index 00000000..06ee062b --- /dev/null +++ b/tests/yaml_samples/drc_unco.kiplot.yaml @@ -0,0 +1,9 @@ +# Example KiPlot config file +kiplot: + version: 1 + +preflight: + run_drc: true + ignore_unconnected: true + + diff --git a/tests/yaml_samples/error_pre_wrong_type_2.kiplot.yaml b/tests/yaml_samples/error_pre_wrong_type_2.kiplot.yaml new file mode 100644 index 00000000..f2ac5b3d --- /dev/null +++ b/tests/yaml_samples/error_pre_wrong_type_2.kiplot.yaml @@ -0,0 +1,10 @@ +# Example KiPlot config file +kiplot: + version: 1 + +preflight: + update_xml: true + run_drc: true + ignore_unconnected: trululu + +