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[PCB/SCH parity] Check for value and fields/properties

This commit is contained in:
Salvador E. Tropea 2023-03-31 08:45:09 -03:00
parent 2f8e416f06
commit 9811972ace
7 changed files with 56 additions and 13 deletions
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2
CHANGELOG.md
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@ -21,6 +21,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- BoM:
- Support for extra information in the *Value* field.
Currently just parsed, not rejected.
- PCB/SCH parity test:
- Check for value and fields/properties.
### Fixed
- Makefile: don't skip all preflights on each run, just the ones we generate

32
kibot/pre_update_xml.py
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@ -10,6 +10,7 @@ Dependencies:
command: eeschema_do
version: 1.5.4
"""
from collections import namedtuple
import os
from sys import exit
import xml.etree.ElementTree as ET
@ -23,6 +24,7 @@ from .optionable import Optionable
import pcbnew
logger = get_logger(__name__)
Component = namedtuple("Component", "val fp props")
class Update_XMLOptions(Optionable):
@ -79,10 +81,27 @@ class Update_XML(BasePreFlight): # noqa: F821
if ref not in comps:
errors.append('{} found in PCB, but not in schematic'.format(ref))
continue
sch_fp = comps[ref]
sch_data = comps[ref]
pcb_fp = m.GetFPIDAsString()
if sch_fp != pcb_fp:
errors.append('{} footprint mismatch (PCB: {} vs schematic: {})'.format(ref, pcb_fp, sch_fp))
if sch_data.fp != pcb_fp:
errors.append('{} footprint mismatch (PCB: `{}` vs schematic: `{}`)'.format(ref, pcb_fp, sch_data.fp))
pcb_val = m.GetValue()
if sch_data.val != pcb_val:
errors.append('{} value mismatch (PCB: `{}` vs schematic: `{}`)'.format(ref, pcb_val, sch_data.val))
# Properties
pcb_props = m.GetProperties()
found_props = set()
for p, v in sch_data.props.items():
v_pcb = pcb_props.get(p)
if v_pcb is None:
errors.append('{} schematic property `{}` not in PCB'.format(ref, p))
continue
found_props.add(p)
if v_pcb != v:
errors.append('{} property mismatch (PCB: `{}` vs schematic: `{}`)'.format(ref, v_pcb, v))
# Missing properties
for p in set(pcb_props.keys()).difference(found_props):
errors.append('{} PCB property `{}` not in schematic'.format(ref, p))
for ref in set(comps.keys()).difference(found_comps):
errors.append('{} found in schematic, but not in PCB'.format(ref))
@ -143,10 +162,13 @@ class Update_XML(BasePreFlight): # noqa: F821
if components is not None:
for c in components.iter('comp'):
ref = c.attrib.get('ref')
val = c.find('value')
val = val.text if val is not None else ''
fp = c.find('footprint')
fp = fp.text if fp is not None else ''
logger.debugl(2, '- {}: {}'.format(ref, fp))
comps[ref] = fp
props = {p.get('name'): p.get('value') for p in c.iter('property')}
logger.debugl(2, '- {}: {} {} {}'.format(ref, val, fp, props))
comps[ref] = Component(val, fp, props)
netlist = root.find('nets')
net_nodes = {}
if netlist is not None:

5
tests/board_samples/kicad_6/pcb_parity.kicad_pcb
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@ -76,6 +76,8 @@
(at 146.3 78.6)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor")
(property "Sheetfile" "pcb_parity.kicad_sch")
(property "Sheetname" "")
(path "/00000000-0000-0000-0000-00005ebe91ac")
(attr smd)
(fp_text reference "C1" (at 0 -1.65) (layer "F.SilkS")
@ -116,6 +118,7 @@
(at 146.3 81.55 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor")
(property "Size" "0805")
(path "/00000000-0000-0000-0000-00005ebe8a2e")
(attr smd)
(fp_text reference "R1" (at 0 -1.65) (layer "F.SilkS")
@ -156,6 +159,8 @@
(at 150.71 78.6 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor")
(property "Sheetfile" "pcb_parity.kicad_sch")
(property "Sheetname" "")
(path "/00000000-0000-0000-0000-00005ebe8e9e")
(attr smd)
(fp_text reference "R2" (at 0 -1.65) (layer "F.SilkS")

11
tests/board_samples/kicad_6/pcb_parity.kicad_sch
View File

@ -312,10 +312,10 @@
(property "Reference" "R1" (id 0) (at 90.678 54.7116 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "100" (id 1) (at 90.678 57.023 0)
(property "Value" "120" (id 1) (at 90.678 57.023 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "Resistor_SMD:R_0805_2012Metric" (id 2) (at 87.122 55.88 90)
(property "Footprint" "Resistor_SMD:R_0603_2012Metric" (id 2) (at 87.122 55.88 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 88.9 55.88 0)
@ -340,6 +340,9 @@
(property "Datasheet" "~" (id 3) (at 88.9 69.85 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Tolerance" "1%" (id 4) (at 88.9 69.85 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid eda12c9f-b24f-4458-a3cc-61f318dc57fe))
(pin "2" (uuid 004d701c-7e69-4a10-9c95-7de04fa2be20))
)
@ -356,7 +359,7 @@
(property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (id 2) (at 100.0252 73.66 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (id 3) (at 99.06 69.85 0)
(property "Datasheet" "bogus.pdf" (id 3) (at 99.06 69.85 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid a86ce70c-0b0b-4e00-81fd-fa720b16c5ec))
@ -506,7 +509,7 @@
(reference "FID1") (unit 1) (value "Fiducial") (footprint "")
)
(path "/00000000-0000-0000-0000-00005ebe8a2e"
(reference "R1") (unit 1) (value "100") (footprint "Resistor_SMD:R_0805_2012Metric")
(reference "R1") (unit 1) (value "120") (footprint "Resistor_SMD:R_0603_2012Metric")
)
(path "/00000000-0000-0000-0000-00005ebe8e9e"
(reference "R2") (unit 1) (value "200") (footprint "Resistor_SMD:R_0805_2012Metric")

5
tests/board_samples/kicad_7/pcb_parity.kicad_pcb
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@ -77,6 +77,8 @@
(at 146.3 78.6)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor")
(property "Sheetfile" "pcb_parity.kicad_sch")
(property "Sheetname" "")
(path "/00000000-0000-0000-0000-00005ebe91ac")
(attr smd)
(fp_text reference "C1" (at 0 -1.65) (layer "F.SilkS")
@ -127,6 +129,7 @@
(at 146.3 81.55 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor")
(property "Size" "0805")
(path "/00000000-0000-0000-0000-00005ebe8a2e")
(attr smd)
(fp_text reference "R1" (at 0 -1.65) (layer "F.SilkS")
@ -177,6 +180,8 @@
(at 150.71 78.6 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor")
(property "Sheetfile" "pcb_parity.kicad_sch")
(property "Sheetname" "")
(path "/00000000-0000-0000-0000-00005ebe8e9e")
(attr smd)
(fp_text reference "R2" (at 0 -1.65) (layer "F.SilkS")

9
tests/board_samples/kicad_7/pcb_parity.kicad_sch
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@ -312,10 +312,10 @@
(property "Reference" "R1" (at 90.678 54.7116 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Value" "100" (at 90.678 57.023 0)
(property "Value" "120" (at 90.678 57.023 0)
(effects (font (size 1.27 1.27)) (justify left))
)
(property "Footprint" "Resistor_SMD:R_0805_2012Metric" (at 87.122 55.88 90)
(property "Footprint" "Resistor_SMD:R_0603_2012Metric" (at 87.122 55.88 90)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (at 88.9 55.88 0)
@ -347,6 +347,9 @@
(property "Datasheet" "~" (at 88.9 69.85 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Tolerance" "1%" (at 88.9 69.85 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid eda12c9f-b24f-4458-a3cc-61f318dc57fe))
(pin "2" (uuid 004d701c-7e69-4a10-9c95-7de04fa2be20))
(instances
@ -370,7 +373,7 @@
(property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 100.0252 73.66 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Datasheet" "~" (at 99.06 69.85 0)
(property "Datasheet" "bogus.pdf" (at 99.06 69.85 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid a86ce70c-0b0b-4e00-81fd-fa720b16c5ec))

5
tests/test_plot/test_preflight.py
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@ -198,13 +198,16 @@ def test_update_xml_2(test_dir):
ctx = context.TestContext(test_dir, prj, 'update_xml_2', '')
# The XML should be created where the schematic is located
xml = os.path.abspath(os.path.join(ctx.get_board_dir(), prj+'.xml'))
ctx.run(ret_val=NETLIST_DIFF)
ctx.run(ret_val=NETLIST_DIFF, extra_debug=True)
# Check all outputs are there
# ctx.expect_out_file(prj+'.csv')
assert os.path.isfile(xml)
assert os.path.getsize(xml) > 0
logging.debug(os.path.basename(xml)+' OK')
ctx.search_err(["C1 footprint mismatch",
"R1 value mismatch .PCB: .100. vs schematic: .120",
"R1 schematic property .Sheetname. not in PCB",
"R1 PCB property .Size. not in schematic ",
"F1 found in PCB, but not in schematic",
"FID1 found in schematic, but not in PCB",
"Net count mismatch .PCB 3 vs schematic 4.",