From 99c826f3d77a691b06190d16d2e2dfbb939fcbcc Mon Sep 17 00:00:00 2001 From: "Salvador E. Tropea" Date: Mon, 1 Nov 2021 10:41:37 -0300 Subject: [PATCH] JLCPCB example, to match current recommendations - See: g200kg/kicad-gerberzipper#11 - Added `route_mode_for_oval_holes` option --- CHANGELOG.md | 3 +++ docs/samples/JLCPCB.kibot.yaml | 7 +++++-- docs/samples/JLCPCB_stencil.kibot.yaml | 7 +++++-- kibot/out_excellon.py | 2 ++ 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f713ea8a..5afd3aeb 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -21,11 +21,14 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 and it contain at least one space, now we try to use the text before the space. This helps for cases like "10K 1%". - Generic filter: options to match if a field is/isn't defined. +- Excellon drill: added `route_mode_for_oval_holes` option. ### Changed - Internal BoM: now components with different Tolerance, Voltage, Current and/or Power fields aren't grouped together. These fields are now part of the default `group_fields`. (#79) +- JLCPCB example, to match current recommendations + (g200kg/kicad-gerberzipper#11) ### Fixed - Position files now defaults to use the auxiliar origin as KiCad. diff --git a/docs/samples/JLCPCB.kibot.yaml b/docs/samples/JLCPCB.kibot.yaml index c11286e0..65fadb75 100644 --- a/docs/samples/JLCPCB.kibot.yaml +++ b/docs/samples/JLCPCB.kibot.yaml @@ -17,7 +17,7 @@ outputs: plot_footprint_values: false force_plot_invisible_refs_vals: false tent_vias: true - use_protel_extensions: false + use_protel_extensions: true create_gerber_job_file: false disable_aperture_macros: true gerber_precision: 4.6 @@ -25,6 +25,7 @@ outputs: use_gerber_net_attributes: false line_width: 0.1 subtract_mask_from_silk: true + inner_extension_pattern: '.gp%n' layers: # Note: a more generic approach is to use 'copper' but then the filenames # are slightly different. @@ -50,7 +51,9 @@ outputs: pth_and_npth_single_file: false pth_id: '-PTH' npth_id: '-NPTH' - metric_units: false + metric_units: true + map: gerber + route_mode_for_oval_holes: false output: "%f%i.%x" - name: JLCPCB diff --git a/docs/samples/JLCPCB_stencil.kibot.yaml b/docs/samples/JLCPCB_stencil.kibot.yaml index 713e4047..fda88cbe 100644 --- a/docs/samples/JLCPCB_stencil.kibot.yaml +++ b/docs/samples/JLCPCB_stencil.kibot.yaml @@ -17,7 +17,7 @@ outputs: plot_footprint_values: false force_plot_invisible_refs_vals: false tent_vias: true - use_protel_extensions: false + use_protel_extensions: true create_gerber_job_file: false disable_aperture_macros: true gerber_precision: 4.6 @@ -25,6 +25,7 @@ outputs: use_gerber_net_attributes: false line_width: 0.1 subtract_mask_from_silk: true + inner_extension_pattern: '.gp%n' layers: - copper - F.SilkS @@ -43,7 +44,9 @@ outputs: pth_and_npth_single_file: false pth_id: '-PTH' npth_id: '-NPTH' - metric_units: false + metric_units: true + map: gerber + route_mode_for_oval_holes: false output: "%f%i.%x" - name: JLCPCB diff --git a/kibot/out_excellon.py b/kibot/out_excellon.py index a7bdc364..6266c119 100644 --- a/kibot/out_excellon.py +++ b/kibot/out_excellon.py @@ -31,11 +31,13 @@ class ExcellonOptions(AnyDrill): """ number of digits for integer part of coordinates (0 is auto) """ self.right_digits = 0 """ number of digits for mantissa part of coordinates (0 is auto) """ + self.route_mode_for_oval_holes = True self._ext = 'drl' def _configure_writer(self, board, offset): drill_writer = EXCELLON_WRITER(board) drill_writer.SetOptions(self.mirror_y_axis, self.minimal_header, offset, self.pth_and_npth_single_file) + drill_writer.SetRouteModeForOvalHoles(self.route_mode_for_oval_holes) drill_writer.SetFormat(self.metric_units, ZF[self.zeros_format], self.left_digits, self.right_digits) self._unified_output = self.pth_and_npth_single_file return drill_writer