diff --git a/CHANGELOG.md b/CHANGELOG.md
index 32f33504..e3c7dbbe 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -23,7 +23,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Problems expanding multiple KiCad variables in the same value.
- XML BoM: Fixed problems with fields containing / (#206)
- pcb_print: vias processing was disabled.
-- pcb_print: frame orientation in GUI mode.
+- pcb_print: problems with frame in GUI mode and portrait page orientation.
+- svg_pcb_print: page orientation for portrait.
### Changed
- KiCad environment variables: more variables detected, native KiCad 6 names,
diff --git a/Makefile b/Makefile
index eebccc0b..af86d4c8 100644
--- a/Makefile
+++ b/Makefile
@@ -74,7 +74,7 @@ test_docker_local_1:
# Also change the owner of the files to the current user (we run as root like in GitHub)
#docker run --rm -it -v $(CWD):$(CWD) --workdir="$(CWD)" setsoft/kicad_auto_test:latest '/bin/bash'
docker run --rm -v $(CWD):$(CWD) --workdir="$(CWD)" setsoft/kicad_auto_test:latest \
- /bin/bash -c "flake8 . --count --statistics ; python3-coverage run -a src/kibot --help-outputs > /dev/null; pytest-3 --log-cli-level debug -k 'test_report_simple_2' --test_dir output ; $(PY_COV) html; chown -R $(USER_ID):$(GROUP_ID) output/ tests/board_samples/ tests/.config/kiplot/plugins/__pycache__/ tests/test_plot/fake_pcbnew/__pycache__/ tests/.config/kibot/plugins/__pycache__/ .coverage htmlcov/"
+ /bin/bash -c "flake8 . --count --statistics ; python3-coverage run -a src/kibot --help-outputs > /dev/null; pytest-3 --log-cli-level debug -k 'test_print_pcb_svg_simple_2' --test_dir output ; $(PY_COV) html; chown -R $(USER_ID):$(GROUP_ID) output/ tests/board_samples/ tests/.config/kiplot/plugins/__pycache__/ tests/test_plot/fake_pcbnew/__pycache__/ tests/.config/kibot/plugins/__pycache__/ .coverage htmlcov/"
#$(PY_COV) report
#x-www-browser htmlcov/index.html
rm .coverage
diff --git a/kibot/kicad/patch_svg.py b/kibot/kicad/patch_svg.py
index 3e3144ad..dd167f80 100644
--- a/kibot/kicad/patch_svg.py
+++ b/kibot/kicad/patch_svg.py
@@ -15,6 +15,9 @@ logger = log.get_logger()
def patch_svg_file(file, remove_bkg=False, is_portrait=False):
""" KiCad always prints in portrait """
+ if is_portrait and not remove_bkg:
+ # Nothing to do
+ return
logger.debug('Patching SVG file `{}`'.format(file))
with open(file, 'rt') as f:
text = f.read()
diff --git a/kibot/out_svg_pcb_print.py b/kibot/out_svg_pcb_print.py
index c2598337..145cd58a 100644
--- a/kibot/out_svg_pcb_print.py
+++ b/kibot/out_svg_pcb_print.py
@@ -8,6 +8,7 @@ from .gs import GS
from .out_any_pcb_print import Any_PCB_PrintOptions, register_deps
from .error import KiPlotConfigurationError
from .kicad.patch_svg import patch_svg_file
+from .kicad.pcb import PCB
from .macros import macros, document, output_class # noqa: F401
from .layer import Layer
from . import log
@@ -34,8 +35,9 @@ class SVG_PCB_PrintOptions(Any_PCB_PrintOptions):
# KiCad 6.0.2 bug: https://gitlab.com/kicad/code/kicad/-/issues/11033
o = self._parent
out_files = o.get_targets(o.expand_dirname(os.path.join(GS.out_dir, o.dir)))
+ is_portrait = PCB.load(GS.pcb_file).paper_portrait
for file in out_files:
- patch_svg_file(file)
+ patch_svg_file(file, is_portrait=is_portrait)
@output_class
diff --git a/tests/board_samples/kicad_6/bom_portrait.kicad_pcb b/tests/board_samples/kicad_6/bom_portrait.kicad_pcb
new file mode 100644
index 00000000..e163ef5c
--- /dev/null
+++ b/tests/board_samples/kicad_6/bom_portrait.kicad_pcb
@@ -0,0 +1,207 @@
+(kicad_pcb (version 20211014) (generator pcbnew)
+
+ (general
+ (thickness 1.6)
+ )
+
+ (paper "A4" portrait)
+ (layers
+ (0 "F.Cu" signal)
+ (31 "B.Cu" signal)
+ (32 "B.Adhes" user "B.Adhesive")
+ (33 "F.Adhes" user "F.Adhesive")
+ (34 "B.Paste" user)
+ (35 "F.Paste" user)
+ (36 "B.SilkS" user "B.Silkscreen")
+ (37 "F.SilkS" user "F.Silkscreen")
+ (38 "B.Mask" user)
+ (39 "F.Mask" user)
+ (40 "Dwgs.User" user "User.Drawings")
+ (41 "Cmts.User" user "User.Comments")
+ (42 "Eco1.User" user "User.Eco1")
+ (43 "Eco2.User" user "User.Eco2")
+ (44 "Edge.Cuts" user)
+ (45 "Margin" user)
+ (46 "B.CrtYd" user "B.Courtyard")
+ (47 "F.CrtYd" user "F.Courtyard")
+ (48 "B.Fab" user)
+ (49 "F.Fab" user)
+ )
+
+ (setup
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 148.4 80.2)
+ (pcbplotparams
+ (layerselection 0x00010fc_ffffffff)
+ (disableapertmacros false)
+ (usegerberextensions false)
+ (usegerberattributes false)
+ (usegerberadvancedattributes false)
+ (creategerberjobfile false)
+ (svguseinch false)
+ (svgprecision 6)
+ (excludeedgelayer true)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15.000000)
+ (dxfpolygonmode true)
+ (dxfimperialunits true)
+ (dxfusepcbnewfont true)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (sketchpadsonfab false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 1)
+ (scaleselection 1)
+ (outputdirectory "")
+ )
+ )
+
+ (net 0 "")
+ (net 1 "GND")
+ (net 2 "Net-(C1-Pad1)")
+ (net 3 "VCC")
+
+ (footprint "Capacitor_SMD:C_0805_2012Metric" (layer "F.Cu")
+ (tedit 5B36C52B) (tstamp 00000000-0000-0000-0000-00005ebea01d)
+ (at 146.3 78.6)
+ (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+ (tags "capacitor")
+ (path "/00000000-0000-0000-0000-00005ebe91ac")
+ (attr smd)
+ (fp_text reference "C1" (at 0 -1.65) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp c974f755-f11c-4e72-9337-9b1b03ad46d6)
+ )
+ (fp_text value "1uF" (at 0 1.65) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 2b79ad18-d7d7-43df-ab38-e75b2da12556)
+ )
+ (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
+ (effects (font (size 0.5 0.5) (thickness 0.08)))
+ (tstamp 5db96da7-af8d-43d8-8dc7-a398bfc8659a)
+ )
+ (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer "F.SilkS") (width 0.12) (tstamp 3076b8ca-409a-4abb-8543-19f45b2d32e7))
+ (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer "F.SilkS") (width 0.12) (tstamp a32b7c78-669e-4058-9e8f-159773d391d1))
+ (fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp 5298dbf1-ff20-463f-b22f-955b234f027b))
+ (fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 5ee42af7-ef65-46ec-93e1-21c0e6077de0))
+ (fp_line (start 1.68 0.95) (end -1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 9aaa51e5-eb42-4e37-9164-e5b31a4cd652))
+ (fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp e610961e-a821-4b86-8c7d-d4cb27796910))
+ (fp_line (start -1 0.6) (end -1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 1ffd0374-60f5-4975-8863-7ed9f29dac0e))
+ (fp_line (start 1 -0.6) (end 1 0.6) (layer "F.Fab") (width 0.1) (tstamp 26a053d6-55aa-4839-adb7-568fd5c066bb))
+ (fp_line (start -1 -0.6) (end 1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 8367eaee-e0ca-41eb-bc30-e532a8b59fdd))
+ (fp_line (start 1 0.6) (end -1 0.6) (layer "F.Fab") (width 0.1) (tstamp e3a76526-d318-4ed9-8120-844abbdc3456))
+ (pad "1" smd roundrect locked (at -0.9375 0) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 2 "Net-(C1-Pad1)") (tstamp 34fb9d00-02b1-48b3-a790-0112e6a08449))
+ (pad "2" smd roundrect locked (at 0.9375 0) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 1 "GND") (tstamp 0336c0d4-c4f4-4020-8380-287f839c852a))
+ (model "${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
+ (offset (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu")
+ (tedit 5B36C52B) (tstamp 00000000-0000-0000-0000-00005ebea02e)
+ (at 146.3 81.55 180)
+ (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+ (tags "resistor")
+ (path "/00000000-0000-0000-0000-00005ebe8a2e")
+ (attr smd)
+ (fp_text reference "R1" (at 0 -1.65) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 7ef0f81b-f6e6-4f07-b717-38c4b1e50a5e)
+ )
+ (fp_text value "100" (at 0 1.65) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 8cd4eec9-ceb5-4b8f-83f2-9a146ee7ddd5)
+ )
+ (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
+ (effects (font (size 0.5 0.5) (thickness 0.08)))
+ (tstamp 93acb41a-3723-4469-9dee-a34acc325774)
+ )
+ (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer "F.SilkS") (width 0.12) (tstamp 39441d2f-6110-4320-92bb-88f09b0de90b))
+ (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer "F.SilkS") (width 0.12) (tstamp ae28541a-0239-4867-9639-a73e46808278))
+ (fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 752a50bd-195a-4ad5-acdb-d18c11a301e4))
+ (fp_line (start 1.68 0.95) (end -1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 757c5363-13ba-436b-9db8-e5dc02596d27))
+ (fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp 91e75b42-fb6a-4a6b-be78-4013b6183b9a))
+ (fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp c76bc75f-8181-4476-9973-7173e45c68ed))
+ (fp_line (start -1 -0.6) (end 1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 337d7915-43e4-4835-8aab-ff527c0de866))
+ (fp_line (start 1 0.6) (end -1 0.6) (layer "F.Fab") (width 0.1) (tstamp 656d7de6-1e65-4eb7-8002-7e680bef80b9))
+ (fp_line (start 1 -0.6) (end 1 0.6) (layer "F.Fab") (width 0.1) (tstamp ba9a410d-1c13-461f-b6a8-eeb7c4c46e58))
+ (fp_line (start -1 0.6) (end -1 -0.6) (layer "F.Fab") (width 0.1) (tstamp fe5b7a7b-9594-494a-8fe7-df5ac5e9fd07))
+ (pad "1" smd roundrect locked (at -0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 3 "VCC") (tstamp ee158b8c-0101-4c4c-b5ce-76e87c497fb9))
+ (pad "2" smd roundrect locked (at 0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 2 "Net-(C1-Pad1)") (tstamp b67e7460-96bc-4aa0-8593-880eb3320d89))
+ (model "${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metrico.step"
+ (offset (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu")
+ (tedit 5B36C52B) (tstamp 00000000-0000-0000-0000-00005ebea03f)
+ (at 150.71 78.6 180)
+ (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+ (tags "resistor")
+ (path "/00000000-0000-0000-0000-00005ebe8e9e")
+ (attr smd)
+ (fp_text reference "R2" (at 0 -1.65) (layer "F.SilkS")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp 9d088aec-c53e-413e-8715-779a6ee7e407)
+ )
+ (fp_text value "200" (at 0 1.65) (layer "F.Fab")
+ (effects (font (size 1 1) (thickness 0.15)))
+ (tstamp abf3504c-c638-4bb0-8898-7b38d0241a11)
+ )
+ (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab")
+ (effects (font (size 0.5 0.5) (thickness 0.08)))
+ (tstamp 730e1bed-bd81-4343-85e9-17d6a47cb046)
+ )
+ (fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer "F.SilkS") (width 0.12) (tstamp 7613df36-4992-4dd5-b97e-1f17e43e73c6))
+ (fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer "F.SilkS") (width 0.12) (tstamp b6f74bca-cdeb-4109-905d-6a81777da69b))
+ (fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp 0e6314c1-5679-49cb-898a-296f9477855a))
+ (fp_line (start 1.68 0.95) (end -1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp 434bf54a-a88a-45dc-a569-a0a5b81a7096))
+ (fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer "F.CrtYd") (width 0.05) (tstamp ea59c7f6-51a1-4630-b89e-075386e527c9))
+ (fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer "F.CrtYd") (width 0.05) (tstamp ee5f10ba-08e8-4cb5-8185-dae7f54c20a3))
+ (fp_line (start -1 0.6) (end -1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 5c2f40eb-308c-4cc2-9669-44b6645a7910))
+ (fp_line (start -1 -0.6) (end 1 -0.6) (layer "F.Fab") (width 0.1) (tstamp 608be37a-af03-4e73-9e8e-c1bb3353eaf4))
+ (fp_line (start 1 -0.6) (end 1 0.6) (layer "F.Fab") (width 0.1) (tstamp a384a468-0937-4800-9a3b-e63b6186898c))
+ (fp_line (start 1 0.6) (end -1 0.6) (layer "F.Fab") (width 0.1) (tstamp dc5732f3-4764-4a19-a8e3-24308ca8b363))
+ (pad "1" smd roundrect locked (at -0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 2 "Net-(C1-Pad1)") (tstamp 55440b89-8f8a-483a-9b2b-9ccc95708f75))
+ (pad "2" smd roundrect locked (at 0.9375 0 180) (size 0.975 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
+ (net 1 "GND") (tstamp 3d8a4e48-dfd4-4c64-8dd3-885d6a7ed460))
+ (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0805_2012Metric.step"
+ (offset (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (gr_line (start 153 84) (end 153 76) (layer "Edge.Cuts") (width 0.05) (tstamp 00000000-0000-0000-0000-00005ebea29b))
+ (gr_line (start 144 76) (end 144 84) (layer "Edge.Cuts") (width 0.05) (tstamp bb3326cd-028c-43fb-af47-5975412a67c7))
+ (gr_line (start 153 76) (end 144 76) (layer "Edge.Cuts") (width 0.05) (tstamp d534140b-6f16-4b83-8893-ef4b026f6ec9))
+ (gr_line (start 144 84) (end 153 84) (layer "Edge.Cuts") (width 0.05) (tstamp ea655683-6135-4d3f-a322-1186e1a703b2))
+
+ (segment (start 147.2375 78.6) (end 149.7725 78.6) (width 0.25) (layer "F.Cu") (net 1) (tstamp 4ebf58f7-8428-4480-b240-bb7d3c895103))
+ (segment (start 150.62249 77.57499) (end 151.161973 78.114473) (width 0.25) (layer "F.Cu") (net 2) (tstamp 4ed009e2-b8f5-47d8-ba45-e73cbf2524c2))
+ (segment (start 145.3625 78.6) (end 145.3625 79.3) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5505e502-12b2-42b0-9e88-71997ebbcbde))
+ (segment (start 151.161973 78.114473) (end 151.6475 78.6) (width 0.25) (layer "F.Cu") (net 2) (tstamp 5e3899fa-1efc-49c7-bd03-0723e6564f66))
+ (segment (start 145.3625 78.6) (end 146.38751 77.57499) (width 0.25) (layer "F.Cu") (net 2) (tstamp 88b2a9f5-ec07-44cc-be7d-6243af8d21a7))
+ (segment (start 145.3625 79.3) (end 145.3625 81.55) (width 0.25) (layer "F.Cu") (net 2) (tstamp a49ce2ce-5d29-415b-a41f-07567cbabb0f))
+ (segment (start 146.38751 77.57499) (end 150.62249 77.57499) (width 0.25) (layer "F.Cu") (net 2) (tstamp fd90cb38-571b-4f7c-8630-139c123989e3))
+
+)
diff --git a/tests/reference/5_1_6/bom_portrait-F_Cu+F_SilkS.svg b/tests/reference/5_1_6/bom_portrait-F_Cu+F_SilkS.svg
new file mode 100644
index 00000000..264e6cb3
--- /dev/null
+++ b/tests/reference/5_1_6/bom_portrait-F_Cu+F_SilkS.svg
@@ -0,0 +1,39 @@
+
+
diff --git a/tests/reference/5_1_7/bom_portrait-F_Cu+F_SilkS.svg b/tests/reference/5_1_7/bom_portrait-F_Cu+F_SilkS.svg
new file mode 120000
index 00000000..43285f6e
--- /dev/null
+++ b/tests/reference/5_1_7/bom_portrait-F_Cu+F_SilkS.svg
@@ -0,0 +1 @@
+../5_1_6/bom_portrait-F_Cu+F_SilkS.svg
\ No newline at end of file
diff --git a/tests/reference/6_0_4/bom_portrait-F_Cu+F_SilkS.svg b/tests/reference/6_0_4/bom_portrait-F_Cu+F_SilkS.svg
new file mode 100644
index 00000000..91924ab4
--- /dev/null
+++ b/tests/reference/6_0_4/bom_portrait-F_Cu+F_SilkS.svg
@@ -0,0 +1,63 @@
+
+
diff --git a/tests/test_plot/test_print_pcb.py b/tests/test_plot/test_print_pcb.py
index 40591c52..2abb5c05 100644
--- a/tests/test_plot/test_print_pcb.py
+++ b/tests/test_plot/test_print_pcb.py
@@ -25,7 +25,7 @@ def test_print_pcb_simple(test_dir):
ctx.clean_up()
-def test_print_pcb_svg_simple(test_dir):
+def test_print_pcb_svg_simple_1(test_dir):
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'print_pcb_svg')
ctx.run()
@@ -36,6 +36,18 @@ def test_print_pcb_svg_simple(test_dir):
ctx.clean_up()
+def test_print_pcb_svg_simple_2(test_dir):
+ """ Check the portrait version is OK """
+ prj = 'bom_portrait'
+ ctx = context.TestContext(test_dir, prj, 'print_pcb_svg')
+ ctx.run()
+ # Check all outputs are there
+ file = prj+'-F_Cu+F_SilkS.svg'
+ ctx.expect_out_file(file)
+ ctx.compare_image(file)
+ ctx.clean_up()
+
+
def test_print_pcb_refill_1(test_dir):
prj = 'zone-refill'
ctx = context.TestContext(test_dir, prj, 'print_pcb_zone-refill')