Modified tests to keep kibom-variant_3.pro

tests/test_plot/test_gerber.py

@@ -114,4 +114,4 @@ def test_gerber_variant_1():
     # variant: test        directory: test        components: R1, R3 and C2
     check_layers_exist(ctx, 'test', prj, ALL_LAYERS, '_(test)')
     check_components(ctx, 'test', prj, ['F_Paste', 'F_Adhes'], '_(test)', ['R2'], ['C1', 'R1', 'R3', 'C2'])
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)

tests/test_plot/test_int_bom.py

@@ -1235,7 +1235,7 @@ def test_int_bom_variant_t2if():
     check_kibom_test_netlist(rows, ref_column, 2, ['C1'], ['R1', 'R2', 'C2'])
     rows, header, info = ctx.load_csv(prj+'-bom_(test).csv')
     check_kibom_test_netlist(rows, ref_column, 2, ['R2'], ['R1', 'C1', 'C2'])
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)
 
 
 def test_int_bom_variant_t2is():
@@ -1245,7 +1245,7 @@ def test_int_bom_variant_t2is():
     rows, header, info = ctx.load_csv('filter_R1.csv')
     ref_column = header.index(REF_COLUMN_NAME)
     check_kibom_test_netlist(rows, ref_column, 1, ['R2', 'R1'], ['C1', 'C2'])
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)
 
 
 def test_int_bom_wrong_variant():
@@ -1297,7 +1297,7 @@ def test_int_bom_fil_2():
     rows, header, info = ctx.load_csv('virtual.csv')
     check_kibom_test_netlist(rows, ref_column, 2, None, ['R1-R2', 'C1-C2'])
     ctx.search_err(r".?R3.? component in board, but not in schematic")
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)
 
 
 def test_int_bom_variant_t3():

tests/test_plot/test_pcbdraw.py

@@ -110,7 +110,7 @@ def test_pcbdraw_variant_1():
     # components was removed.
     # Expected: R1 and R2 populated
     ctx.compare_image(fname, fuzz='30%')
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)
 
 
 def test_pcbdraw_variant_2():
@@ -122,7 +122,7 @@ def test_pcbdraw_variant_2():
     ctx.expect_out_file(fname)
     # Expected: R1 and R2 populated + C1 manually added
     ctx.compare_image(fname, fuzz='30%')
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)
 
 
 def test_pcbdraw_variant_3():
@@ -134,4 +134,4 @@ def test_pcbdraw_variant_3():
     ctx.expect_out_file(fname)
     ctx.compare_image(fname, fuzz='30%')
     assert ctx.search_err("Ambiguous list of components to show .?none.? vs variant/filter")
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)

tests/test_plot/test_position.py

@@ -179,4 +179,4 @@ def test_position_variant_t2i():
     check_comps(rows, ['C2', 'R1', 'R2', 'R3'])
     rows, header, info = ctx.load_csv(prj+'-both_pos_(test).csv')
     check_comps(rows, ['C1', 'C2', 'R1', 'R3'])
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)

tests/test_plot/test_print_pcb.py

@@ -50,7 +50,7 @@ def test_print_variant_1():
     ctx.search_err(r'KiCad project file not found', True)
     ctx.expect_out_file(fname)
     ctx.compare_pdf(fname)
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)
 
 
 def test_print_pcb_options():

tests/test_plot/test_step.py

@@ -55,4 +55,4 @@ def test_step_variant_1():
     ctx.run()
     # Check all outputs are there
     ctx.expect_out_file(prj+'-3D.step')
-    ctx.clean_up()
+    ctx.clean_up(keep_project=True)

tests/utils/context.py

@@ -138,14 +138,14 @@ class TestContext(object):
             self._del_dir_after = True
         logging.info('Output dir: '+self.output_dir)
 
-    def clean_up(self):
+    def clean_up(self, keep_project=False):
         logging.debug('Clean-up')
         if self._del_dir_after:
             logging.debug('Removing dir')
             shutil.rmtree(self.output_dir)
         # We don't have a project, and we don't want one
         pro = os.path.join(self.get_board_dir(), self.board_name+'.pro')
-        if os.path.isfile(pro):
+        if os.path.isfile(pro) and not keep_project:
             os.remove(pro)
         # We don't have a footprint cache, and we don't want one
         fp_cache = os.path.join(self.get_board_dir(), 'fp-info-cache')