Added report contexts to expand individual layers

kibot/out_report.py

@@ -270,6 +270,32 @@ class ReportOptions(BaseOptions):
         """ Replace iterator for the `schematic_svgs` context """
         return self._context_images(line, self._schematic_svgs)
 
+    def _context_individual_images(self, line, images):
+        """ Replace iterator for the various contexts that expands one image """
+        text = ''
+        context = {'new_line': '\n'}
+        for s in images:
+            context['path_'+s[2]] = s[0]
+            context['comment_'+s[2]] = s[1]
+        text += self.do_replacements(line, context)
+        return text
+
+    def context_layer_pdf(self, line):
+        """ Replace iterator for the `layer_pdf` context """
+        return self._context_individual_images(line, self._layer_pdfs)
+
+    def context_layer_svg(self, line):
+        """ Replace iterator for the `layer_svg` context """
+        return self._context_individual_images(line, self._layer_svgs)
+
+    def context_schematic_pdf(self, line):
+        """ Replace iterator for the `schematic_pdf` context """
+        return self._context_individual_images(line, self._schematic_pdfs)
+
+    def context_schematic_svg(self, line):
+        """ Replace iterator for the `schematic_svg` context """
+        return self._context_individual_images(line, self._schematic_svgs)
+
     @staticmethod
     def is_pure_smd_5(m):
         return m.GetAttributes() == UI_SMD
@@ -579,7 +605,7 @@ class ReportOptions(BaseOptions):
                 out_files = o.get_targets(o.expand_dirname(os.path.join(GS.out_dir, o.dir)))
                 for of in out_files:
                     rel_path = os.path.relpath(of, base_dir)
-                    dest.append((rel_path, o.comment))
+                    dest.append((rel_path, o.comment, o.name))
         self.layer_pdfs = len(self._layer_pdfs) > 0
         self.layer_svgs = len(self._layer_svgs) > 0
         self.schematic_pdfs = len(self._schematic_pdfs) > 0

kibot/report_templates/report_simple.txt

@@ -1,16 +1,24 @@
 PCB Specifications:
 Size:
+
 - ${bb_w_mm}x${bb_h_mm} mm
 
 Class: ${pattern_class}${drill_class}
+
 Track width: ≥ ${track_mm} mm
+
 Insulation distance: ≥ ${clearance_mm} mm
+
 Minimum drill size: ≥ ${drill_mm} mm (finished metalized hole: ${drill_1_mm} mm)
+
 Minimum slot width: ≥ ${slot_mm} mm
+
 Ring collar: ≥ ${oar_mm} mm
 
 #?edge_connector or castellated_pads or edge_plating
 Special features:
+#?edge_connector or castellated_pads or edge_plating
+
 #?edge_connector
 - Edge connector: ${edge_connector}
 #?castellated_pads
@@ -20,8 +28,12 @@ Special features:
 
 #?stackup
 Stackup:
+#?stackup and impedance_controlled
+
 #?stackup and impedance_controlled
 Impedance controlled: YES
+#?stackup
+
 #?stackup
 | Name                 | Type                 | Color    | Thickness | Material        | Epsilon_r | Loss tangent |
 #?stackup
@@ -31,18 +43,26 @@ Impedance controlled: YES
 #?stackup
 
 Materials:
+
 - ${pcb_material}, ${thickness_mm} mm
 - ${pcb_finish}
 - ${layers} layers
 - ${copper_thickness} µm copper thickness
 
 Solder mask:
+
 - ${solder_mask}
 - ${solder_mask_color_text}
 
 Marking:
+
 - ${silk_screen} screen printing
 - Silk: ${silk_screen_color_text}
 
 Other markings:
+
 - ROHS / UL / Date - Yes if available
+
+PCB:
+
+#layer_svg:![${comment_print_front}](${path_print_front}){ width=16.5cm height=11.7cm }

tests/reference/5_1_6/light_control-report_simple.txt

@@ -1,28 +1,42 @@
 PCB Specifications:
 Size:
+
 - 59.69x48.26 mm
 
 Class: 6D
+
 Track width: ≥ 0.15 mm
+
 Insulation distance: ≥ 0.15 mm
+
 Minimum drill size: ≥ 0.25 mm (finished metalized hole: 0.15 mm)
+
 Minimum slot width: ≥ 0.6 mm
+
 Ring collar: ≥ 0.25 mm
 
 
 Materials:
+
 - FR4, 1.6 mm
 - ENIG
 - 4 layers
 - 35 µm copper thickness
 
 Solder mask:
+
 - TOP / BOTTOM
 - Top: Blue / Bottom: Red
 
 Marking:
+
 - TOP / BOTTOM screen printing
 - Silk: White
 
 Other markings:
+
 - ROHS / UL / Date - Yes if available
+
+PCB:
+
+![Top copper and silkscreen](Layers/light_control-F_Cu+F_SilkS.svg){ width=16.5cm height=11.7cm }

tests/reference/6_0_0/light_control-report_simple.txt

@@ -1,21 +1,30 @@
 PCB Specifications:
 Size:
+
 - 59.69x48.26 mm
 
 Class: 6D
+
 Track width: ≥ 0.15 mm
+
 Insulation distance: ≥ 0.15 mm
+
 Minimum drill size: ≥ 0.25 mm (finished metalized hole: 0.15 mm)
+
 Minimum slot width: ≥ 0.6 mm
+
 Ring collar: ≥ 0.25 mm
 
 Special features:
+
 - Edge connector: yes, bevelled
 - Castellated pads
 - Edge plating
 
 Stackup:
+
 Impedance controlled: YES
+
 | Name                 | Type                 | Color    | Thickness | Material        | Epsilon_r | Loss tangent |
 |----------------------|----------------------|----------|-----------|-----------------|-----------|--------------|
 | F.SilkS              | Top Silk Screen      | White    |           | Liquid Photo    |           |              |
@@ -33,18 +42,26 @@ Impedance controlled: YES
 | B.SilkS              | Bottom Silk Screen   | Black    |           | Direct Printing |           |              |
 
 Materials:
+
 - FR4, 1.6 mm
 - ENIG
 - 4 layers
 - 35 µm copper thickness
 
 Solder mask:
+
 - TOP / BOTTOM
 - Top: Blue / Bottom: Red
 
 Marking:
+
 - TOP / BOTTOM screen printing
 - Silk: Top: White / Bottom: Black
 
 Other markings:
+
 - ROHS / UL / Date - Yes if available
+
+PCB:
+
+![Top copper and silkscreen](Layers/light_control-F_Cu+F_SilkS.svg){ width=16.5cm height=11.7cm }