From b5fc7e8c55632e64ffe509a8d7a30b289c279bc6 Mon Sep 17 00:00:00 2001 From: "Salvador E. Tropea" Date: Mon, 25 Jul 2022 11:40:24 -0300 Subject: [PATCH] [Report] Fixed converted file wasn't stored at `dir` Closes #238 --- CHANGELOG.md | 2 + kibot/out_report.py | 5 +- .../5_1_6/light_control-report.txt_2 | 6 +- .../6_0_4/light_control-report.txt_2 | 138 +++++++++++++++++- tests/test_plot/test_misc.py | 7 +- tests/yaml_samples/report_simple_2.kibot.yaml | 1 + 6 files changed, 150 insertions(+), 9 deletions(-) mode change 120000 => 100644 tests/reference/6_0_4/light_control-report.txt_2 diff --git a/CHANGELOG.md b/CHANGELOG.md index 2c1f7999..c91295b9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -24,6 +24,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Problems with zones on multiple layers (#226) - SCH Variants on KiCad 6: - Problems with missing values in the title block. +- Report: + - Converted file wasn't stored at `dir` (#238) ### Changed - The order in which main sections are parsed is now fixed. diff --git a/kibot/out_report.py b/kibot/out_report.py index 48d2139a..a1901b4d 100644 --- a/kibot/out_report.py +++ b/kibot/out_report.py @@ -730,9 +730,10 @@ class ReportOptions(BaseOptions): if not self.do_convert: return command = self.ensure_tool('PanDoc') - out = self.expand_converted_output(GS.out_dir) + dir_out = os.path.dirname(os.path.abspath(fname)) + out = self.expand_converted_output(dir_out) logger.debug('Converting the report to: {}'.format(out)) - resources = '--resource-path='+GS.out_dir + resources = '--resource-path='+dir_out # Pandoc 2.2.1 doesn't support "--to pdf" if not out.endswith('.'+self.convert_to): logger.warning(W_WRONGEXT+'The conversion tool detects the output format using the extension') diff --git a/tests/reference/5_1_6/light_control-report.txt_2 b/tests/reference/5_1_6/light_control-report.txt_2 index 85f9a55e..d1a4f774 100644 --- a/tests/reference/5_1_6/light_control-report.txt_2 +++ b/tests/reference/5_1_6/light_control-report.txt_2 @@ -102,13 +102,13 @@ Drill tools (including vias and computing adjusts and rounding): # Schematic -![Schematic](Schematic.svg){ width=16.5cm height=11.7cm } +![Schematic](../Schematic.svg){ width=16.5cm height=11.7cm } # PCB Layers -![Top copper and silkscreen](Layers/light_control-assembly-front.pdf){ width=16.5cm height=11.7cm } +![Top copper and silkscreen](../Layers/light_control-assembly-front.pdf){ width=16.5cm height=11.7cm } -![Bottom copper and silkscreen](Layers/light_control-assembly-bottom.pdf){ width=16.5cm height=11.7cm } +![Bottom copper and silkscreen](../Layers/light_control-assembly-bottom.pdf){ width=16.5cm height=11.7cm } diff --git a/tests/reference/6_0_4/light_control-report.txt_2 b/tests/reference/6_0_4/light_control-report.txt_2 deleted file mode 120000 index 6fcf20ac..00000000 --- a/tests/reference/6_0_4/light_control-report.txt_2 +++ /dev/null @@ -1 +0,0 @@ -light_control-report.txt \ No newline at end of file diff --git a/tests/reference/6_0_4/light_control-report.txt_2 b/tests/reference/6_0_4/light_control-report.txt_2 new file mode 100644 index 00000000..4791a406 --- /dev/null +++ b/tests/reference/6_0_4/light_control-report.txt_2 @@ -0,0 +1,137 @@ +# PCB + +Board size: 59.69x48.26 mm (2.35x1.9 inches) + +- This is the size of the rectangle that contains the board +- Thickness: 1.6 mm (63 mils) +- Material: FR4 +- Finish: ENIG +- Layers: 4 +- Copper thickness: 35 µm + +Solder mask: TOP / BOTTOM + +- Color: Top: Blue / Bottom: Red + +Silk screen: TOP / BOTTOM + +- Color: Top: White / Bottom: Black + +Special features: + +- Edge connector: yes, bevelled +- Castellated pads +- Edge plating + +Stackup: + +Impedance controlled: YES + +| Name | Type | Color | Thickness | Material | Epsilon_r | Loss tangent | +|----------------------|----------------------|----------|-----------|-----------------|-----------|--------------| +| F.SilkS | Top Silk Screen | White | | Liquid Photo | | | +| F.Paste | Top Solder Paste | | | | | | +| F.Mask | Top Solder Mask | Blue | 10 | Liquid Ink | 3.3 | 0.00 | +| F.Cu | copper | | 35 | | | | +| dielectric 1 | prepreg | | 480 | FR4 | 4.5 | 0.02 | +| In1.Cu | copper | | 35 | | | | +| dielectric 2 | core | | 480 | FR4 | 4.5 | 0.02 | +| In2.Cu | copper | | 35 | | | | +| dielectric 3 | prepreg | | 480 | FR4 | 4.5 | 0.02 | +| B.Cu | copper | | 35 | | | | +| B.Mask | Bottom Solder Mask | Red | 10 | Dry Film | 3.3 | 0.00 | +| B.Paste | Bottom Solder Paste | | | | | | +| B.SilkS | Bottom Silk Screen | Black | | Direct Printing | | | + +# Important sizes + +Clearance: 0.15 mm (6 mils) + +Track width: 0.15 mm (6 mils) + +- By design rules: 0.13 mm (5 mils) + +Drill: 0.35 mm (14 mils) + +- Vias: 0.35 mm (14 mils) [Design: 0.3 mm (12 mils)] +- Pads: 0.7 mm (28 mils) +- The above values are real drill sizes, they add 0.1 mm (4 mils) to plated holes (PTH) + +Via: 0.51/0.25 mm (20/10 mils) + +- By design rules: 0.46/0.2 mm (18/8 mils) +- Micro via: no [0.2/0.1 mm (8/4 mils)] +- Burried/blind via: no + +Outer Annular Ring: 0.08 mm (3 mils) + +- By design rules: 0.08 mm (3 mils) + +Eurocircuits class: 10C + + +# General stats + +Components count: (SMD/THT) + +- Top: 61/12 (SMD + THT) +- Bottom: 0/0 (NONE) + +Defined tracks: + +- 0.15 mm (6 mils) +- 0.3 mm (12 mils) +- 0.64 mm (25 mils) + +Used tracks: + +- 0.15 mm (6 mils) (276) defined: yes +- 0.3 mm (12 mils) (11) defined: yes +- 0.64 mm (25 mils) (175) defined: yes + +Defined vias: + +- 0.51/0.25 mm (20/10 mils) +- 0.89/0.51 mm (35/20 mils) + +Used vias: + +- 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes +- 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes + +Holes (excluding vias): + +- 0.8 mm (31 mils) (4) +- 0.85 mm (33 mils) (2) +- 0.95 mm (37 mils) (3) +- 1.2 mm (47 mils) (20) +- 3.2 mm (126 mils) (4) + +Oval holes: + +- 0.6x1.3 mm (24x51 mils) (2) + +Drill tools (including vias and computing adjusts and rounding): + +- 0.35 mm (14 mils) (23) +- 0.6 mm (24 mils) (33) +- 0.7 mm (28 mils) (2) +- 0.9 mm (35 mils) (4) +- 0.95 mm (37 mils) (2) +- 1.05 mm (41 mils) (3) +- 1.3 mm (51 mils) (20) +- 3.2 mm (126 mils) (4) + + +# Schematic + +![Schematic](../Schematic.svg){ width=16.5cm height=11.7cm } + + + +# PCB Layers + +![Top copper and silkscreen](../Layers/light_control-assembly-front.pdf){ width=16.5cm height=11.7cm } + +![Bottom copper and silkscreen](../Layers/light_control-assembly-bottom.pdf){ width=16.5cm height=11.7cm } + diff --git a/tests/test_plot/test_misc.py b/tests/test_plot/test_misc.py index d9ceb3bb..dd2b8ebc 100644 --- a/tests/test_plot/test_misc.py +++ b/tests/test_plot/test_misc.py @@ -1009,11 +1009,12 @@ def test_report_simple_2(test_dir): prj = 'light_control' ctx = context.TestContext(test_dir, prj, 'report_simple_2', POS_DIR) ctx.run() - ctx.expect_out_file(prj+'-report.txt') + f_report = os.path.join('report', prj+'-report.txt') + ctx.expect_out_file(f_report) ctx.expect_out_file(prj+'-report_simple.txt') - ctx.compare_txt(prj+'-report.txt', prj+'-report.txt_2') + ctx.compare_txt(f_report, prj+'-report.txt_2') ctx.compare_txt(prj+'-report_simple.txt') - ctx.expect_out_file(prj+'-report.pdf') + ctx.expect_out_file(f_report.replace('.txt', '.pdf')) ctx.clean_up(keep_project=True) diff --git a/tests/yaml_samples/report_simple_2.kibot.yaml b/tests/yaml_samples/report_simple_2.kibot.yaml index b34b3f6b..8ca699f8 100644 --- a/tests/yaml_samples/report_simple_2.kibot.yaml +++ b/tests/yaml_samples/report_simple_2.kibot.yaml @@ -54,5 +54,6 @@ outputs: - name: 'report_full' comment: "Full design report" type: report + dir: report options: do_convert: true