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[Fixed] Spell errors

This commit is contained in:
Salvador E. Tropea 2024-01-05 09:09:58 -03:00
parent 950a875c33
commit d7392d59ec
13 changed files with 19 additions and 19 deletions
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2
.pre-commit-config.yaml
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@ -78,7 +78,7 @@ repos:
# hooks:
# - id: isort
- repo: https://github.com/codespell-project/codespell
rev: v2.1.0
rev: v2.2.6
hooks:
- id: codespell
# - repo: https://github.com/pre-commit/mirrors-mypy

4
CHANGELOG.md
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@ -217,7 +217,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
get the old behavior.
- Git diff link file name:
- Now we default to using worktrees instead of stash push/pop. As a side
effect the names of the git points are chnaged. This is because main/master
effect the names of the git points are changed. This is because main/master
only applies to the main worktree. So the names now refer to the closest
tag.
- JLCPCB_stencil: Is now just like JLCPCB. The only difference is the added
@ -973,7 +973,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
internal BoM. They are usually mistakes that prevents grouping components.
### Fixed
- The variants logic for BoMs when a component resquested to be only added to
- The variants logic for BoMs when a component requested to be only added to
more than one variant.
- Removed warnings about malformed values for DNF components indicating it in
its value.

2
docs/1_SCH_2_part_PCBs/README.md
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@ -83,7 +83,7 @@ Filter B:
![Schematic](Hierarchy_1/Filter_B/Generated/Filter_B-assembly_page_02.png)
In order to create a schematic for the whole system you create a third project.
In this project you use hierarchichal sheets to join both projects and show
In this project you use hierarchical sheets to join both projects and show
how they are connected.
![Schematic](Hierarchy_1/Top_Level/Generated/Schematic.svg)

2
kibot/kicad/v5_sch.py
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@ -1927,7 +1927,7 @@ class Schematic(object):
def save_netlist_components(self, root, comps, excluded, fitted, no_field):
""" Generates the `components` section of the netlist """
components = SubElement(root, 'components')
# Colapse units
# Collapse units
real_comps = []
tstamps = {}
for c in comps:

2
kibot/mcpyrate/quotes.py
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@ -274,7 +274,7 @@ def capture_value(value, name):
# whether the captured value is used in the current process, or in another
# Python process later.
#
# If the macro expansion result is to remain available for re-use from a
# If the macro expansion result is to remain available for reuse from a
# `.pyc`, we must serialize and store the captured value to disk, so that
# values from "macro expansion time last week" are still available when the
# `.pyc` is loaded in another Python process later.

4
kibot/out_base.py
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@ -327,7 +327,7 @@ class VariantOptions(BaseOptions):
brect = Rect()
c = comps_hash.get(ref, None)
if c and c.included and not c.fitted:
# Meassure the component BBox (only graphics)
# Measure the component BBox (only graphics)
for gi in m.GraphicalItems():
if gi.GetClass() == GS.footprint_gr_type:
l_gi = gi.GetLayer()
@ -419,7 +419,7 @@ class VariantOptions(BaseOptions):
old_c_layers.append(pad_layers.FmtHex())
pad_layers.removeLayerSet(exclude)
if len(pad_layers.Seq()) == 0:
# No layers at all. Ridiculous, but happends.
# No layers at all. Ridiculous, but happens.
# At least add an F.Mask
pad_layers.addLayer(fmask if is_front else bmask)
logger.warning(W_WRONGPASTE+'Pad with solder paste, but no copper or solder mask aperture in '+ref)

2
kibot/out_blender_export.py
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@ -220,7 +220,7 @@ class BlenderPointOfViewOptions(Optionable):
""" *[top,bottom,front,rear,right,left,z,Z,y,Y,x,X] Point of view.
Compatible with `render_3d` """
self.file_id = ''
""" String to diferentiate the name of this point of view.
""" String to differentiate the name of this point of view.
When empty we use the `default_file_id` or the `view` """
self.steps = 1
""" [1-1000] Generate this amount of steps using the rotation angles as increments.

2
kibot/out_bom.py
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@ -1029,7 +1029,7 @@ class BoM(BaseOutput): # noqa: F821
fld_names_l = [f.lower() for f in fld_names]
fld_set = set(fld_names_l)
logger.debug(' - Available fields {}'.format(fld_names_l))
# Look for the manufaturer part number
# Look for the manufacturer part number
mpn_set = {k for k, v in KICOST_NAME_TRANSLATIONS.items() if v == 'manf#'}
mpn_set.add('manf#')
mpn_fields = fld_set.intersection(mpn_set)

4
kibot/out_diff.py
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@ -76,7 +76,7 @@ class DiffOptions(VariantOptions):
""" Directory to cache the intermediate files. Leave it blank to disable the cache """
self.diff_mode = 'red_green'
""" [red_green,stats] In the `red_green` mode added stuff is green and red when removed.
The `stats` mode is used to meassure the amount of difference. In this mode all
The `stats` mode is used to measure the amount of difference. In this mode all
changes are red, but you can abort if the difference is bigger than certain threshold """
self.fuzz = 5
""" [0,100] Color tolerance (fuzzyness) for the `stats` mode """
@ -102,7 +102,7 @@ class DiffOptions(VariantOptions):
`file_id` instead of its name """
self.only_different = False
""" Only include the pages with differences in the output PDF.
Note that when no differeces are found we get a page saying *No diff* """
Note that when no differences are found we get a page saying *No diff* """
self.only_first_sch_page = False
""" Compare only the main schematic page (root page) """
self.always_fail_if_missing = False

2
kibot/out_pcbdraw.py
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@ -241,7 +241,7 @@ class PcbDrawOptions(VariantOptions):
self.show_solderpaste = True
""" Show the solder paste layers """
self.resistor_remap = PcbDrawResistorRemap
""" [list(dict)] List of resitors to be remapped. You can change the value of the resistors here """
""" [list(dict)] List of resistors to be remapped. You can change the value of the resistors here """
self.resistor_flip = Optionable
""" [string|list(string)=''] List of resistors to flip its bands """
self.size_detection = 'kicad_edge'

2
kibot/out_populate.py
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@ -70,7 +70,7 @@ class PopulateOptions(VariantOptions):
raise KiPlotConfigurationError('Missing input file `{}`'.format(self.input))
# Initial components
self.initial_components = Optionable.force_list(self.initial_components)
# Validate the image patter name
# Validate the image pattern name
if '%d' not in self.imgname:
raise KiPlotConfigurationError('The image pattern must contain `%d` `{}`'.format(self.imgname))

2
kibot/svgutils/transform.py
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@ -182,7 +182,7 @@ class TextElement(FigureElement):
class ImageElement(FigureElement):
"""Inline image element.
Correspoonds to SVG ``<image>`` tag. Image data encoded as base64 string.
Corresponds to SVG ``<image>`` tag. Image data encoded as base64 string.
"""
def __init__(self, stream, width, height, format="png"):

8
tests/test_plot/test_misc.py
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@ -914,7 +914,7 @@ def test_compress_sources_1(test_dir):
def test_date_format_1(test_dir):
""" Date from SCH reformated """
""" Date from SCH reformatted """
prj = 'test_v5'
ctx = context.TestContext(test_dir, prj, 'date_format_1')
ctx.run(extra=[])
@ -923,7 +923,7 @@ def test_date_format_1(test_dir):
def test_date_format_2(test_dir):
""" Date from SCH reformated """
""" Date from SCH reformatted """
prj = 'bom'
ctx = context.TestContext(test_dir, prj, 'date_format_1')
ctx.run(extra=[])
@ -1044,7 +1044,7 @@ def test_report_simple_2(test_dir):
def test_report_edge_1(test_dir):
""" Meassures the PCB size when using a component that contains the real PCB edges #164 """
""" Measures the PCB size when using a component that contains the real PCB edges #164 """
prj = 'comp_edge'
ctx = context.TestContext(test_dir, prj, 'report_edge_1', POS_DIR)
ctx.run()
@ -1055,7 +1055,7 @@ def test_report_edge_1(test_dir):
@pytest.mark.skipif(context.ki5(), reason="Example in KiCad 6 format")
def test_report_edge_2(test_dir):
""" Meassures the PCB size when using circles in the PCB edge #375 """
""" Measures the PCB size when using circles in the PCB edge #375 """
prj = 'circle_edge'
ctx = context.TestContext(test_dir, prj, 'report_edge_1', POS_DIR)
ctx.run()