215 lines
6.2 KiB
Python
215 lines
6.2 KiB
Python
"""
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Tests miscellaneous stuff.
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- -s all -i
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- -s run_erc,update_xml,run_drc -i
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- -s all,run_drc
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- -s bogus
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- An unknown output type
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- -s all and_one_of_two_outs
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- Missing schematic
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- Wrong PCB name
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- Missing PCB
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- Missing config
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- Wrong config name
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- Guess the PCB and YAML
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- Guess the PCB and YAML when more than one is present
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- --list
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For debug information use:
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pytest-3 --log-cli-level debug
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"""
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import os
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import sys
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import shutil
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# Look for the 'utils' module from where the script is running
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prev_dir = os.path.dirname(os.path.abspath(__file__))
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sys.path.insert(0, os.path.dirname(prev_dir))
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# Utils import
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from utils import context
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sys.path.insert(0, os.path.dirname(prev_dir))
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from kiplot.misc import (EXIT_BAD_ARGS, EXIT_BAD_CONFIG, NO_SCH_FILE, NO_PCB_FILE)
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POS_DIR = 'positiondir'
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def test_skip_pre_and_outputs():
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prj = 'simple_2layer'
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ctx = context.TestContext('SkipPreAndPos', prj, 'pre_and_position', POS_DIR)
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ctx.run(extra=['-s', 'all', '-i'])
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ctx.dont_expect_out_file(ctx.get_pos_both_csv_filename())
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assert ctx.search_err('Skipping all pre-flight actions')
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assert ctx.search_err('Skipping all outputs')
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ctx.clean_up()
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def test_skip_pre_and_outputs_2():
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prj = 'simple_2layer'
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ctx = context.TestContext('SkipPreAndPos2', prj, 'pre_and_position', POS_DIR)
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ctx.run(extra=['-s', 'run_erc,update_xml,run_drc', '-i'])
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ctx.dont_expect_out_file(ctx.get_pos_both_csv_filename())
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assert ctx.search_err('Skipping run_erc')
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assert ctx.search_err('Skipping run_drc')
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assert ctx.search_err('Skipping update_xml')
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assert ctx.search_err('Skipping all outputs')
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ctx.clean_up()
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def test_skip_pre_and_outputs_3():
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prj = 'simple_2layer'
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ctx = context.TestContext('SkipPreAndPos3', prj, 'pre_and_position', POS_DIR)
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ctx.run(EXIT_BAD_ARGS, extra=['-s', 'all,run_drc'])
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ctx.dont_expect_out_file(ctx.get_pos_both_csv_filename())
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assert ctx.search_err('Use `--skip all`')
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ctx.clean_up()
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def test_skip_pre_and_outputs_4():
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prj = 'simple_2layer'
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ctx = context.TestContext('SkipPreAndPos4', prj, 'pre_and_position', POS_DIR)
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ctx.run(EXIT_BAD_ARGS, extra=['-s', 'bogus'])
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ctx.dont_expect_out_file(ctx.get_pos_both_csv_filename())
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assert ctx.search_err('Unknown action to skip: bogus')
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ctx.clean_up()
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def test_unknown_out():
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prj = 'simple_2layer'
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ctx = context.TestContext('UnknownOut', prj, 'unknown_out', POS_DIR)
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ctx.run(EXIT_BAD_CONFIG)
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ctx.dont_expect_out_file(ctx.get_pos_both_csv_filename())
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assert ctx.search_err("Unknown output type 'bogus'")
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ctx.clean_up()
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def test_select_output():
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prj = '3Rs'
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ctx = context.TestContext('DoASCIISkipCSV', prj, 'pre_and_position', POS_DIR)
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ctx.run(extra=['-s', 'all', 'pos_ascii'])
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ctx.dont_expect_out_file(ctx.get_pos_both_csv_filename())
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ctx.expect_out_file(ctx.get_pos_both_filename())
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assert ctx.search_err('Skipping position output')
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ctx.clean_up()
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def test_miss_sch():
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prj = '3Rs'
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ctx = context.TestContext('MissingSCH', prj, 'pre_and_position', POS_DIR)
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ctx.run(NO_SCH_FILE, extra=['pos_ascii'])
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assert ctx.search_err('Missing schematic')
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ctx.clean_up()
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def test_miss_pcb():
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prj = '3Rs'
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ctx = context.TestContext('MissingPCB', prj, 'pre_and_position', POS_DIR)
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ctx.board_file = 'bogus'
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ctx.run(NO_PCB_FILE, extra=['-s', 'run_erc,update_xml', 'pos_ascii'])
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assert ctx.search_err('Board file not found')
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ctx.clean_up()
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def test_miss_pcb_2():
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ctx = context.TestContext('MissingPCB_2', '3Rs', 'pre_and_position', POS_DIR)
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ctx.run(EXIT_BAD_ARGS, no_board_file=True)
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assert ctx.search_err('No PCB file found')
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ctx.clean_up()
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def test_miss_yaml():
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prj = '3Rs'
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ctx = context.TestContext('MissingYaml', prj, 'pre_and_position', POS_DIR)
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ctx.run(EXIT_BAD_ARGS, no_yaml_file=True)
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assert ctx.search_err('No config file')
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ctx.clean_up()
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def test_miss_yaml_2():
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prj = '3Rs'
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ctx = context.TestContext('MissingYaml_wrong', prj, 'pre_and_position', POS_DIR)
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ctx.yaml_file = 'bogus'
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ctx.run(EXIT_BAD_ARGS)
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assert ctx.search_err('Plot config file not found: bogus')
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ctx.clean_up()
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def test_auto_pcb_and_cfg():
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prj = '3Rs'
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ctx = context.TestContext('GuessPCB_cfg', prj, 'pre_and_position', POS_DIR)
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board_file = os.path.basename(ctx.board_file)
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shutil.copy2(ctx.board_file, ctx.get_out_path(board_file))
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yaml_file = os.path.basename(ctx.yaml_file)
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shutil.copy2(ctx.yaml_file, ctx.get_out_path(yaml_file))
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ctx.run(extra=['-s', 'all', '-i', 'pos_ascii'], no_out_dir=True, no_board_file=True, no_yaml_file=True, chdir_out=True)
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ctx.dont_expect_out_file(ctx.get_pos_both_filename())
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ctx.expect_out_file(ctx.get_pos_both_csv_filename())
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assert ctx.search_err('Using PCB file: '+board_file)
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assert ctx.search_err('Using config file: '+yaml_file)
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ctx.clean_up()
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def test_auto_pcb_and_cfg_2():
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prj = '3Rs'
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ctx = context.TestContext('GuessPCB_cfg_rep', prj, 'pre_and_position', POS_DIR)
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board_file = os.path.basename(ctx.board_file)
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shutil.copy2(ctx.board_file, ctx.get_out_path(board_file))
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shutil.copy2(ctx.board_file, ctx.get_out_path('b_'+board_file))
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yaml_file = os.path.basename(ctx.yaml_file)
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shutil.copy2(ctx.yaml_file, ctx.get_out_path(yaml_file))
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shutil.copy2(ctx.yaml_file, ctx.get_out_path('b_'+yaml_file))
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ctx.run(extra=['-s', 'all', '-i', 'pos_ascii'], no_out_dir=True, no_board_file=True, no_yaml_file=True, chdir_out=True)
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assert ctx.search_err('WARNING:More than one PCB')
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assert ctx.search_err('WARNING:More than one config')
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m = ctx.search_err('Using (.*).kicad_pcb')
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assert m
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ctx.board_name = m.group(1)
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ctx.dont_expect_out_file(ctx.get_pos_both_filename())
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ctx.expect_out_file(ctx.get_pos_both_csv_filename())
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ctx.clean_up()
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def test_list():
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ctx = context.TestContext('List', '3Rs', 'pre_and_position', POS_DIR)
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ctx.run(extra=['--list'])
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assert ctx.search_err('run_erc: True')
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assert ctx.search_err('run_drc: True')
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assert ctx.search_err('update_xml: True')
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assert ctx.search_err(r'position \(Pick and place file\) \[position\]')
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assert ctx.search_err(r'pos_ascii \(Pick and place file\) \[position\]')
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ctx.clean_up()
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