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Correct the minimum via size for JLCPCB

This commit is contained in:
Marco Massarelli 2024-01-26 18:36:47 +00:00
parent e13af5c0ac
commit 53152dc586
1 changed files with 2 additions and 2 deletions
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4
ergogen/footprints/sk6812mini-e.js
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@ -13,8 +13,8 @@ module.exports = {
gnd_trace_width: 0.25, // Max 0.8 to avoid clearance errors
pwr_trace_width: 0.25, // Max 0.8 to avoid clearance errors
signal_trace_width: 0.15,
via_size: 0.8, // JLCPC min is 0.5 for 1-2 layer boards, KiCad defaults to 0.8
via_drill: 0.4, // JLCPC min is 0.3 for 1-2 layer boards, KiCad defaults to 0.4
via_size: 0.8, // JLCPCB min is 0.56 for 1-2 layer boards, KiCad defaults to 0.8
via_drill: 0.4, // JLCPCB min is 0.3 for 1-2 layer boards, KiCad defaults to 0.4
side: 'B',
},
body: p => {