The 'check_zone_fills' option is now independent of 'run_drc'
Implemented in a different way. For all internal commands now we use Python bindings to fill the zones as suggested by @arikrupnik in johnbeard/kiplot#11 For 'print_pcb' now we ask KiCad to do it before printing (needs v1.4.1)
This commit is contained in:
Salvador E. Tropea
parent
406a9ab374
commit
0d9256fb24
|
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@ -9,9 +9,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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### Added
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- Better debug information when a BoM fails to be generated.
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- Support for compressed YAML files.
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### Changed
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- Allowed operations that doesn't involve a PCB now can run if the PCB file is
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missing or corrupted.
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- The 'check_zone_fills' option is now independent of 'run_drc'
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### Fixed
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- Error codes that overlapped.
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12
Makefile
12
Makefile
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@ -1,10 +1,11 @@
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#!/usr/bin/make
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PY_COV=python3-coverage
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REFDIR=tests/reference/
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REFILL=tests/board_samples/zone-refill.kicad_pcb
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CWD := $(abspath $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
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USER_ID=$(shell id -u)
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GROUP_ID=$(shell id -g)
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deb:
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fakeroot dpkg-buildpackage -uc -b
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@ -43,4 +44,11 @@ test_docker_local:
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deb_clean:
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fakeroot debian/rules clean
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.PHONY: deb deb_clean lint test test_local
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gen_ref:
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# Reference outputs, must be manually inspected if regenerated
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cp -a $(REFILL).refill $(REFILL)
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src/kiplot -c tests/yaml_samples/pdf_zone-refill.kiplot.yaml -b tests/board_samples/zone-refill.kicad_pcb -d $(REFDIR)
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src/kiplot -c tests/yaml_samples/print_pcb_zone-refill.kiplot.yaml -b tests/board_samples/zone-refill.kicad_pcb -d $(REFDIR)
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cp -a $(REFILL).ok $(REFILL)
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.PHONY: deb deb_clean lint test test_local gen_ref
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@ -51,9 +51,9 @@ This section is used to specify tasks that will executed before generating any o
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- `run_erc` To run the ERC (Electrical Rules Check). To ensure the schematic is electrically correct.
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- `run_drc` To run the DRC (Distance Rules Check). To ensure we have a valid PCB.
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- `update_xml` To update the XML version of the BoM (Bill of Materials). To ensure our generated BoM is up to date.
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- `check_zone_fills` Zones are filled before doing any operation involving PCB layers.
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The `run_drc` command has the following options:
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- `check_zone_fills` Every time we run the DRC the zones are filled again. This option saves the PCB to disk updating the zones.
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The `run_drc` command has the following option:
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- `ignore_unconnected` Ignores the unconnected nets. Useful if you didn't finish the routing.
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Here is an example of a *preflight* section:
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@ -169,7 +169,6 @@ outputs:
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plot_footprint_values: true
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force_plot_invisible_refs_vals: false
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tent_vias: true
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check_zone_fills: true
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line_width: 0.15
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# gerber options
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@ -199,7 +198,6 @@ Most options are the same you'll find in the KiCad dialogs.
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- `plot_footprint_values` include the footprint values
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- `force_plot_invisible_refs_vals` include references and values even when they are marked as invisible
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- `tent_vias` cover the vias
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- `check_zone_fills` currently without effect
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Note that each layer is generated in a separated file.
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@ -134,6 +134,8 @@ class Plotter(object):
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def _load_board(self, brd_file):
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try:
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board = pcbnew.LoadBoard(brd_file)
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if self.cfg.check_zone_fills:
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pcbnew.ZONE_FILLER(board).Fill(board.Zones())
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except OSError as e:
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logger.error('Error loading PCB file. Currupted?')
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logger.error(e)
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@ -165,6 +167,9 @@ class Plotter(object):
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elif skip == 'run_erc':
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self.cfg.run_erc = False
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logger.debug('Skipping run_erc')
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elif skip == 'check_zone_fills':
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self.cfg.check_zone_fills = False
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logger.debug('Skipping run_erc')
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else:
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logger.error('Unknown action to skip: '+skip)
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exit(misc.EXIT_BAD_ARGS)
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@ -179,8 +184,7 @@ class Plotter(object):
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if self.cfg.update_xml:
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self._update_xml(brd_file)
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if self.cfg.run_drc:
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self._run_drc(brd_file, self.cfg.ignore_unconnected,
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self.cfg.check_zone_fills, filter_file)
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self._run_drc(brd_file, self.cfg.ignore_unconnected, filter_file)
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def _run_erc(self, brd_file, filter_file):
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sch_file = check_eeschema_do(brd_file)
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@ -216,7 +220,7 @@ class Plotter(object):
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logger.error('Failed to update the BoM, error %d', ret)
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exit(misc.BOM_ERROR)
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def _run_drc(self, brd_file, ignore_unconnected, check_zone_fills, filter_file):
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def _run_drc(self, brd_file, ignore_unconnected, filter_file):
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check_script(misc.CMD_PCBNEW_RUN_DRC, misc.URL_PCBNEW_RUN_DRC, '1.4.0')
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cmd = [misc.CMD_PCBNEW_RUN_DRC, 'run_drc']
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if filter_file:
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@ -228,8 +232,6 @@ class Plotter(object):
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cmd.insert(1, '-r')
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if ignore_unconnected:
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cmd.insert(1, '-i')
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if check_zone_fills:
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cmd.insert(1, '-s')
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logger.info('- Running the DRC')
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logger.debug('Executing: '+str(cmd))
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ret = call(cmd)
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@ -602,7 +604,7 @@ class Plotter(object):
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def _do_pcb_print(self, board, output_dir, output, brd_file):
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check_script(misc.CMD_PCBNEW_PRINT_LAYERS,
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misc.URL_PCBNEW_PRINT_LAYERS, '1.3.1')
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misc.URL_PCBNEW_PRINT_LAYERS, '1.4.1')
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to = output.options.type_options
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# Verify the inner layers
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layer_cnt = board.GetCopperLayerCount()
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@ -615,8 +617,10 @@ class Plotter(object):
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"Inner layer {} is not valid for this board"
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.format(layer.layer))
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cmd = [misc.CMD_PCBNEW_PRINT_LAYERS, 'export',
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'--output_name', to.output_name,
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brd_file, output_dir]
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'--output_name', to.output_name]
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if self.cfg.check_zone_fills:
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cmd.append('-f')
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cmd.extend([brd_file, output_dir])
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if level_debug():
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cmd.insert(1, '-vv')
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cmd.insert(1, '-r')
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@ -0,0 +1,339 @@
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(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2~bpo10+1)
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(general
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(thickness 1.6)
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(drawings 5)
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(tracks 10)
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(zones 0)
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(modules 4)
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(nets 4)
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)
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(page A4)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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(45 Margin user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.2)
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(via_size 0.8)
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(via_drill 0.4)
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(via_min_size 0.4)
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(via_min_drill 0.3)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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(edge_width 0.05)
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(segment_width 0.2)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.12)
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(mod_text_size 1 1)
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(mod_text_width 0.15)
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(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.051)
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(solder_mask_min_width 0.25)
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(aux_axis_origin 0 0)
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(visible_elements FFFFFF7F)
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(pcbplotparams
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(layerselection 0x010fc_ffffffff)
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(usegerberextensions false)
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(usegerberattributes false)
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(usegerberadvancedattributes false)
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(creategerberjobfile false)
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(excludeedgelayer true)
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(linewidth 0.100000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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||||
(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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||||
(psnegative false)
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||||
(psa4output false)
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||||
(plotreference true)
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||||
(plotvalue true)
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||||
(plotinvisibletext false)
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||||
(padsonsilk false)
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||||
(subtractmaskfromsilk false)
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||||
(outputformat 1)
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||||
(mirror false)
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||||
(drillshape 1)
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||||
(scaleselection 1)
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||||
(outputdirectory ""))
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||||
)
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||||
|
||||
(net 0 "")
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||||
(net 1 GND)
|
||||
(net 2 "Net-(C1-Pad1)")
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||||
(net 3 "Net-(J1-Pad1)")
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||||
|
||||
(net_class Default "Esta es la clase de red por defecto."
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||||
(clearance 0.2)
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||||
(trace_width 0.25)
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||||
(via_dia 0.8)
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||||
(via_drill 0.4)
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||||
(uvia_dia 0.3)
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||||
(uvia_drill 0.1)
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||||
(add_net GND)
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||||
(add_net "Net-(C1-Pad1)")
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||||
(add_net "Net-(J1-Pad1)")
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||||
)
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||||
|
||||
(module Resistor_SMD:R_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC712)
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||||
(at 161.9375 74 180)
|
||||
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
|
||||
(tags resistor)
|
||||
(path /5EBAD9A3)
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||||
(attr smd)
|
||||
(fp_text reference R1 (at 0 1.65) (layer B.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text value R (at 0 -1.65) (layer B.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text user %R (at 0 0) (layer B.Fab)
|
||||
(effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
|
||||
)
|
||||
(fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
|
||||
(fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
|
||||
(fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
|
||||
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
|
||||
(net 3 "Net-(J1-Pad1)"))
|
||||
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
|
||||
(net 2 "Net-(C1-Pad1)"))
|
||||
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
|
||||
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC57B)
|
||||
(at 167 77.54 180)
|
||||
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
|
||||
(tags "Through hole pin header THT 1x02 2.54mm single row")
|
||||
(path /5EBAC9BE)
|
||||
(fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_01x02_Male (at -4 4.87) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 0 1.27 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
|
||||
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||
(net 2 "Net-(C1-Pad1)"))
|
||||
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||
(net 1 GND))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
|
||||
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC6B7)
|
||||
(at 157.82 74.85)
|
||||
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
|
||||
(tags "Through hole pin header THT 1x02 2.54mm single row")
|
||||
(path /5EBAC114)
|
||||
(fp_text reference J1 (at 0 -2.33) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_01x02_Male (at -4.82 5.15) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 0 1.27 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
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@ -0,0 +1,339 @@
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(kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2~bpo10+1)
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||||
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||||
(general
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
(page A4)
|
||||
(layers
|
||||
(0 F.Cu signal)
|
||||
(31 B.Cu signal)
|
||||
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||||
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||||
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||||
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||||
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||||
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(49 F.Fab user)
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||||
)
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(net 0 "")
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(net 1 GND)
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||||
(net 2 "Net-(C1-Pad1)")
|
||||
(net 3 "Net-(J1-Pad1)")
|
||||
|
||||
(net_class Default "Esta es la clase de red por defecto."
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(add_net GND)
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(add_net "Net-(C1-Pad1)")
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(add_net "Net-(J1-Pad1)")
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||||
)
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||||
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||||
(module Resistor_SMD:R_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC712)
|
||||
(at 161.9375 74 180)
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||||
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
|
||||
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||||
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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(fp_text user %R (at 0 0) (layer B.Fab)
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||||
(fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
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(fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
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(fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
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|
||||
|
||||
(general
|
||||
(thickness 1.6)
|
||||
(drawings 5)
|
||||
(tracks 10)
|
||||
(zones 0)
|
||||
(modules 4)
|
||||
(nets 4)
|
||||
)
|
||||
|
||||
(page A4)
|
||||
(layers
|
||||
(0 F.Cu signal)
|
||||
(31 B.Cu signal)
|
||||
(32 B.Adhes user)
|
||||
(33 F.Adhes user)
|
||||
(34 B.Paste user)
|
||||
(35 F.Paste user)
|
||||
(36 B.SilkS user)
|
||||
(37 F.SilkS user)
|
||||
(38 B.Mask user)
|
||||
(39 F.Mask user)
|
||||
(40 Dwgs.User user)
|
||||
(41 Cmts.User user)
|
||||
(42 Eco1.User user)
|
||||
(43 Eco2.User user)
|
||||
(44 Edge.Cuts user)
|
||||
(45 Margin user)
|
||||
(46 B.CrtYd user)
|
||||
(47 F.CrtYd user)
|
||||
(48 B.Fab user)
|
||||
(49 F.Fab user)
|
||||
)
|
||||
|
||||
(setup
|
||||
(last_trace_width 0.25)
|
||||
(trace_clearance 0.2)
|
||||
(zone_clearance 0.508)
|
||||
(zone_45_only no)
|
||||
(trace_min 0.2)
|
||||
(via_size 0.8)
|
||||
(via_drill 0.4)
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||||
(via_min_size 0.4)
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||||
(via_min_drill 0.3)
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||||
(uvia_size 0.3)
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||||
(uvia_drill 0.1)
|
||||
(uvias_allowed no)
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||||
(uvia_min_size 0.2)
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||||
(uvia_min_drill 0.1)
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||||
(edge_width 0.05)
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||||
(segment_width 0.2)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.12)
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||||
(mod_text_size 1 1)
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||||
(mod_text_width 0.15)
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||||
(pad_size 1.524 1.524)
|
||||
(pad_drill 0.762)
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||||
(pad_to_mask_clearance 0.051)
|
||||
(solder_mask_min_width 0.25)
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||||
(aux_axis_origin 0 0)
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||||
(visible_elements FFFFFF7F)
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||||
(pcbplotparams
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||||
(layerselection 0x010fc_ffffffff)
|
||||
(usegerberextensions false)
|
||||
(usegerberattributes false)
|
||||
(usegerberadvancedattributes false)
|
||||
(creategerberjobfile false)
|
||||
(excludeedgelayer true)
|
||||
(linewidth 0.100000)
|
||||
(plotframeref false)
|
||||
(viasonmask false)
|
||||
(mode 1)
|
||||
(useauxorigin false)
|
||||
(hpglpennumber 1)
|
||||
(hpglpenspeed 20)
|
||||
(hpglpendiameter 15.000000)
|
||||
(psnegative false)
|
||||
(psa4output false)
|
||||
(plotreference true)
|
||||
(plotvalue true)
|
||||
(plotinvisibletext false)
|
||||
(padsonsilk false)
|
||||
(subtractmaskfromsilk false)
|
||||
(outputformat 1)
|
||||
(mirror false)
|
||||
(drillshape 1)
|
||||
(scaleselection 1)
|
||||
(outputdirectory ""))
|
||||
)
|
||||
|
||||
(net 0 "")
|
||||
(net 1 GND)
|
||||
(net 2 "Net-(C1-Pad1)")
|
||||
(net 3 "Net-(J1-Pad1)")
|
||||
|
||||
(net_class Default "Esta es la clase de red por defecto."
|
||||
(clearance 0.2)
|
||||
(trace_width 0.25)
|
||||
(via_dia 0.8)
|
||||
(via_drill 0.4)
|
||||
(uvia_dia 0.3)
|
||||
(uvia_drill 0.1)
|
||||
(add_net GND)
|
||||
(add_net "Net-(C1-Pad1)")
|
||||
(add_net "Net-(J1-Pad1)")
|
||||
)
|
||||
|
||||
(module Resistor_SMD:R_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC712)
|
||||
(at 161.9375 74 180)
|
||||
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
|
||||
(tags resistor)
|
||||
(path /5EBAD9A3)
|
||||
(attr smd)
|
||||
(fp_text reference R1 (at 0 1.65) (layer B.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text value R (at 0 -1.65) (layer B.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text user %R (at 0 0) (layer B.Fab)
|
||||
(effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
|
||||
)
|
||||
(fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
|
||||
(fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
|
||||
(fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
|
||||
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
|
||||
(net 3 "Net-(J1-Pad1)"))
|
||||
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
|
||||
(net 2 "Net-(C1-Pad1)"))
|
||||
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0805_2012Metric.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
|
||||
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC57B)
|
||||
(at 167 77.54 180)
|
||||
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
|
||||
(tags "Through hole pin header THT 1x02 2.54mm single row")
|
||||
(path /5EBAC9BE)
|
||||
(fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_01x02_Male (at -4 4.87) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 0 1.27 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
|
||||
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||
(net 2 "Net-(C1-Pad1)"))
|
||||
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||
(net 1 GND))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
|
||||
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5EBAC6B7)
|
||||
(at 157.82 74.85)
|
||||
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
|
||||
(tags "Through hole pin header THT 1x02 2.54mm single row")
|
||||
(path /5EBAC114)
|
||||
(fp_text reference J1 (at 0 -2.33) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value Conn_01x02_Male (at -4.82 5.15) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text user %R (at 0 1.27 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
|
||||
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||
(net 1 GND))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
|
||||
(net 3 "Net-(J1-Pad1)"))
|
||||
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
|
||||
(module Capacitor_SMD:C_0805_2012Metric (layer B.Cu) (tedit 5B36C52B) (tstamp 5EBAC54F)
|
||||
(at 163 77.0625 270)
|
||||
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
|
||||
(tags capacitor)
|
||||
(path /5EBAE412)
|
||||
(attr smd)
|
||||
(fp_text reference C1 (at 0 1.65 270) (layer B.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text value C (at 0 -1.65 270) (layer B.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text user %R (at 0 0 270) (layer B.Fab)
|
||||
(effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
|
||||
)
|
||||
(fp_line (start 1.68 -0.95) (end -1.68 -0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.68 0.95) (end 1.68 -0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.68 0.95) (end 1.68 0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.68 -0.95) (end -1.68 0.95) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -0.258578 -0.71) (end 0.258578 -0.71) (layer B.SilkS) (width 0.12))
|
||||
(fp_line (start -0.258578 0.71) (end 0.258578 0.71) (layer B.SilkS) (width 0.12))
|
||||
(fp_line (start 1 -0.6) (end -1 -0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start 1 0.6) (end 1 -0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start -1 0.6) (end 1 0.6) (layer B.Fab) (width 0.1))
|
||||
(fp_line (start -1 -0.6) (end -1 0.6) (layer B.Fab) (width 0.1))
|
||||
(pad 2 smd roundrect (at 0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
|
||||
(net 1 GND))
|
||||
(pad 1 smd roundrect (at -0.9375 0 270) (size 0.975 1.4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
|
||||
(net 2 "Net-(C1-Pad1)"))
|
||||
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 0))
|
||||
)
|
||||
)
|
||||
|
||||
(gr_line (start 170 80) (end 169 80) (layer Edge.Cuts) (width 0.05) (tstamp 5EBAC92C))
|
||||
(gr_line (start 170 72) (end 170 80) (layer Edge.Cuts) (width 0.05))
|
||||
(gr_line (start 155 72) (end 170 72) (layer Edge.Cuts) (width 0.05))
|
||||
(gr_line (start 155 80) (end 155 72) (layer Edge.Cuts) (width 0.05))
|
||||
(gr_line (start 169 80) (end 155 80) (layer Edge.Cuts) (width 0.05))
|
||||
|
||||
(segment (start 162.39 77.39) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
|
||||
(segment (start 157.82 77.39) (end 162.39 77.39) (width 0.25) (layer B.Cu) (net 1))
|
||||
(segment (start 163.46 77.54) (end 163 78) (width 0.25) (layer B.Cu) (net 1))
|
||||
(segment (start 167 77.54) (end 163.46 77.54) (width 0.25) (layer B.Cu) (net 1))
|
||||
(segment (start 167 75) (end 164 75) (width 0.25) (layer B.Cu) (net 2))
|
||||
(segment (start 164 75) (end 163 76) (width 0.25) (layer B.Cu) (net 2))
|
||||
(segment (start 164 75) (end 163 74) (width 0.25) (layer B.Cu) (net 2))
|
||||
(segment (start 159.7 74) (end 161 74) (width 0.25) (layer B.Cu) (net 3))
|
||||
(segment (start 157.82 74.85) (end 158.92 74.85) (width 0.25) (layer B.Cu) (net 3))
|
||||
(segment (start 158.92 74.85) (end 159.7 74) (width 0.25) (layer B.Cu) (net 3))
|
||||
|
||||
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 5EBAC970) (hatch edge 0.508)
|
||||
(connect_pads (clearance 0.508))
|
||||
(min_thickness 0.254)
|
||||
(fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
|
||||
(polygon
|
||||
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|
||||
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||||
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||||
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||||
(xy 165.560498 78.63418) (xy 165.619463 78.744494) (xy 165.698815 78.841185) (xy 165.795506 78.920537) (xy 165.90582 78.979502)
|
||||
(xy 166.025518 79.015812) (xy 166.15 79.028072) (xy 166.71425 79.025) (xy 166.873 78.86625) (xy 166.873 77.667)
|
||||
(xy 167.127 77.667) (xy 167.127 78.86625) (xy 167.28575 79.025) (xy 167.85 79.028072) (xy 167.974482 79.015812)
|
||||
(xy 168.09418 78.979502) (xy 168.204494 78.920537) (xy 168.301185 78.841185) (xy 168.380537 78.744494) (xy 168.439502 78.63418)
|
||||
(xy 168.475812 78.514482) (xy 168.488072 78.39) (xy 168.485 77.82575) (xy 168.32625 77.667) (xy 167.127 77.667)
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||||
(xy 166.873 77.667) (xy 165.67375 77.667) (xy 165.515 77.82575) (xy 165.511928 78.39) (xy 164.336588 78.39)
|
||||
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|
||||
(xy 161.665 78.28575) (xy 161.661928 78.4875) (xy 158.809719 78.4875) (xy 158.917588 78.390269) (xy 159.091641 78.15692)
|
||||
(xy 159.216825 77.894099) (xy 159.261476 77.74689) (xy 159.140155 77.517) (xy 157.947 77.517) (xy 157.693 77.517)
|
||||
(xy 156.499845 77.517) (xy 156.378524 77.74689) (xy 155.66 77.74689) (xy 155.66 74) (xy 156.331928 74)
|
||||
(xy 156.331928 75.7) (xy 156.344188 75.824482) (xy 156.380498 75.94418) (xy 156.439463 76.054494) (xy 156.518815 76.151185)
|
||||
(xy 156.615506 76.230537) (xy 156.72582 76.289502) (xy 156.806466 76.313966) (xy 156.722412 76.389731) (xy 156.548359 76.62308)
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||||
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||||
(xy 157.947 77.243) (xy 157.947 77.263) (xy 159.140155 77.263) (xy 159.261476 77.03311) (xy 159.216825 76.885901)
|
||||
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||||
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||||
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||||
(xy 159.460001 75.390001) (xy 159.494163 75.348374) (xy 159.964226 74.836127) (xy 160.023042 74.946164) (xy 160.132708 75.079792)
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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(xy 164.270947 76.706209) (xy 164.321128 76.540785) (xy 164.338072 76.36875) (xy 164.338072 75.88125) (xy 164.32613 75.76)
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
(xy 159.463788 73.277456) (xy 159.407753 73.294454) (xy 159.393257 73.302202) (xy 159.37775 73.307643) (xy 159.32735 73.337431)
|
||||
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|
||||
(xy 159.125845 73.501616) (xy 159.099137 73.530721) (xy 159.024494 73.469463) (xy 158.91418 73.410498) (xy 158.794482 73.374188)
|
||||
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|
||||
(xy 156.518815 73.548815) (xy 156.439463 73.645506) (xy 156.380498 73.75582) (xy 156.344188 73.875518) (xy 156.331928 74)
|
||||
(xy 155.66 74) (xy 155.66 72.66) (xy 169.34 72.66)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -29,3 +29,13 @@ def test_pdf():
|
|||
ctx.dont_expect_out_file(ctx.get_gerber_job_filename())
|
||||
|
||||
ctx.clean_up()
|
||||
|
||||
|
||||
def test_pdf_refill():
|
||||
prj = 'zone-refill'
|
||||
ctx = context.TestContext('Plot_PDF_Refill', prj, 'pdf_zone-refill', '')
|
||||
ctx.run()
|
||||
|
||||
b_cu = ctx.get_gerber_filename('B_Cu', '.pdf')
|
||||
ctx.expect_out_file(b_cu)
|
||||
ctx.compare_image(b_cu)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ from utils import context
|
|||
|
||||
PDF_DIR = 'Layers'
|
||||
PDF_FILE = 'PCB_Top.pdf'
|
||||
PDF_FILE_B = 'PCB_Bot.pdf'
|
||||
|
||||
|
||||
def test_print_pcb():
|
||||
|
|
@ -28,3 +29,12 @@ def test_print_pcb():
|
|||
# Check all outputs are there
|
||||
ctx.expect_out_file(os.path.join(PDF_DIR, PDF_FILE))
|
||||
ctx.clean_up()
|
||||
|
||||
|
||||
def test_print_pcb_refill():
|
||||
prj = 'zone-refill'
|
||||
ctx = context.TestContext('PrPCB_Refill', prj, 'print_pcb_zone-refill', '')
|
||||
ctx.run()
|
||||
|
||||
ctx.expect_out_file(PDF_FILE_B)
|
||||
ctx.compare_image(PDF_FILE_B)
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@ from pty import openpty
|
|||
COVERAGE_SCRIPT = 'python3-coverage'
|
||||
KICAD_PCB_EXT = '.kicad_pcb'
|
||||
KICAD_SCH_EXT = '.sch'
|
||||
REF_DIR = 'N/A'
|
||||
REF_DIR = 'tests/reference'
|
||||
|
||||
|
||||
MODE_SCH = 1
|
||||
MODE_PCB = 0
|
||||
|
|
@ -57,7 +58,7 @@ class TestContext(object):
|
|||
def _get_yaml_name(self, name, yaml_compressed):
|
||||
self.yaml_file = os.path.abspath(os.path.join(self._get_yaml_dir(), name+'.kiplot.yaml'))
|
||||
if yaml_compressed:
|
||||
self.yaml_file += '.gz'
|
||||
self.yaml_file += '.gz'
|
||||
logging.info('YAML file: '+self.yaml_file)
|
||||
assert os.path.isfile(self.yaml_file)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,31 @@
|
|||
kiplot:
|
||||
version: 1
|
||||
|
||||
preflight:
|
||||
check_zone_fills: true
|
||||
|
||||
outputs:
|
||||
- name: PDF
|
||||
comment: "PDF files"
|
||||
type: pdf
|
||||
dir: .
|
||||
options:
|
||||
exclude_edge_layer: false
|
||||
exclude_pads_from_silkscreen: false
|
||||
use_aux_axis_as_origin: false
|
||||
plot_sheet_reference: false
|
||||
plot_footprint_refs: true
|
||||
plot_footprint_values: true
|
||||
force_plot_invisible_refs_vals: false
|
||||
tent_vias: true
|
||||
check_zone_fills: true
|
||||
|
||||
# PDF options
|
||||
drill_marks: small
|
||||
mirror_plot: false
|
||||
negative_plot: false
|
||||
line_width: 0.01
|
||||
layers:
|
||||
- layer: B.Cu
|
||||
suffix: B_Cu
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# Example KiPlot config file
|
||||
kiplot:
|
||||
version: 1
|
||||
|
||||
preflight:
|
||||
check_zone_fills: true
|
||||
|
||||
outputs:
|
||||
- name: 'print_front'
|
||||
comment: "Print B.Cu (filling zones)"
|
||||
type: pdf_pcb_print
|
||||
dir: .
|
||||
options:
|
||||
output_name: PCB_Bot.pdf
|
||||
layers:
|
||||
- layer: B.Cu
|
||||
|
||||
Loading…
Reference in New Issue