Salvador E. Tropea
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30f708db0e
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b5fc7e8c55
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@ -24,6 +24,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- Problems with zones on multiple layers (#226)
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- SCH Variants on KiCad 6:
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- Problems with missing values in the title block.
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- Report:
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- Converted file wasn't stored at `dir` (#238)
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### Changed
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- The order in which main sections are parsed is now fixed.
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@ -730,9 +730,10 @@ class ReportOptions(BaseOptions):
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if not self.do_convert:
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return
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command = self.ensure_tool('PanDoc')
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out = self.expand_converted_output(GS.out_dir)
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dir_out = os.path.dirname(os.path.abspath(fname))
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out = self.expand_converted_output(dir_out)
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logger.debug('Converting the report to: {}'.format(out))
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resources = '--resource-path='+GS.out_dir
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resources = '--resource-path='+dir_out
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# Pandoc 2.2.1 doesn't support "--to pdf"
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if not out.endswith('.'+self.convert_to):
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logger.warning(W_WRONGEXT+'The conversion tool detects the output format using the extension')
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@ -102,13 +102,13 @@ Drill tools (including vias and computing adjusts and rounding):
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# Schematic
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{ width=16.5cm height=11.7cm }
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{ width=16.5cm height=11.7cm }
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# PCB Layers
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{ width=16.5cm height=11.7cm }
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{ width=16.5cm height=11.7cm }
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{ width=16.5cm height=11.7cm }
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{ width=16.5cm height=11.7cm }
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@ -1 +0,0 @@
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light_control-report.txt
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@ -0,0 +1,137 @@
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# PCB
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Board size: 59.69x48.26 mm (2.35x1.9 inches)
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- This is the size of the rectangle that contains the board
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- Thickness: 1.6 mm (63 mils)
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- Material: FR4
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- Finish: ENIG
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- Layers: 4
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- Copper thickness: 35 µm
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Solder mask: TOP / BOTTOM
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- Color: Top: Blue / Bottom: Red
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Silk screen: TOP / BOTTOM
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- Color: Top: White / Bottom: Black
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Special features:
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- Edge connector: yes, bevelled
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- Castellated pads
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- Edge plating
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Stackup:
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Impedance controlled: YES
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| Name | Type | Color | Thickness | Material | Epsilon_r | Loss tangent |
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|----------------------|----------------------|----------|-----------|-----------------|-----------|--------------|
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| F.SilkS | Top Silk Screen | White | | Liquid Photo | | |
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| F.Paste | Top Solder Paste | | | | | |
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| F.Mask | Top Solder Mask | Blue | 10 | Liquid Ink | 3.3 | 0.00 |
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| F.Cu | copper | | 35 | | | |
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| dielectric 1 | prepreg | | 480 | FR4 | 4.5 | 0.02 |
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| In1.Cu | copper | | 35 | | | |
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| dielectric 2 | core | | 480 | FR4 | 4.5 | 0.02 |
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| In2.Cu | copper | | 35 | | | |
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| dielectric 3 | prepreg | | 480 | FR4 | 4.5 | 0.02 |
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| B.Cu | copper | | 35 | | | |
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| B.Mask | Bottom Solder Mask | Red | 10 | Dry Film | 3.3 | 0.00 |
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| B.Paste | Bottom Solder Paste | | | | | |
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| B.SilkS | Bottom Silk Screen | Black | | Direct Printing | | |
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# Important sizes
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Clearance: 0.15 mm (6 mils)
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Track width: 0.15 mm (6 mils)
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- By design rules: 0.13 mm (5 mils)
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Drill: 0.35 mm (14 mils)
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- Vias: 0.35 mm (14 mils) [Design: 0.3 mm (12 mils)]
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- Pads: 0.7 mm (28 mils)
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- The above values are real drill sizes, they add 0.1 mm (4 mils) to plated holes (PTH)
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Via: 0.51/0.25 mm (20/10 mils)
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- By design rules: 0.46/0.2 mm (18/8 mils)
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- Micro via: no [0.2/0.1 mm (8/4 mils)]
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- Burried/blind via: no
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Outer Annular Ring: 0.08 mm (3 mils)
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- By design rules: 0.08 mm (3 mils)
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Eurocircuits class: 10C
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# General stats
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Components count: (SMD/THT)
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- Top: 61/12 (SMD + THT)
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- Bottom: 0/0 (NONE)
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Defined tracks:
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- 0.15 mm (6 mils)
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- 0.3 mm (12 mils)
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- 0.64 mm (25 mils)
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Used tracks:
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- 0.15 mm (6 mils) (276) defined: yes
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- 0.3 mm (12 mils) (11) defined: yes
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- 0.64 mm (25 mils) (175) defined: yes
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Defined vias:
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- 0.51/0.25 mm (20/10 mils)
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- 0.89/0.51 mm (35/20 mils)
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Used vias:
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- 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes
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- 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes
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Holes (excluding vias):
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- 0.8 mm (31 mils) (4)
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- 0.85 mm (33 mils) (2)
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- 0.95 mm (37 mils) (3)
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- 1.2 mm (47 mils) (20)
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- 3.2 mm (126 mils) (4)
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Oval holes:
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- 0.6x1.3 mm (24x51 mils) (2)
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Drill tools (including vias and computing adjusts and rounding):
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- 0.35 mm (14 mils) (23)
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- 0.6 mm (24 mils) (33)
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- 0.7 mm (28 mils) (2)
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- 0.9 mm (35 mils) (4)
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- 0.95 mm (37 mils) (2)
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- 1.05 mm (41 mils) (3)
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- 1.3 mm (51 mils) (20)
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- 3.2 mm (126 mils) (4)
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# Schematic
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{ width=16.5cm height=11.7cm }
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# PCB Layers
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{ width=16.5cm height=11.7cm }
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{ width=16.5cm height=11.7cm }
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@ -1009,11 +1009,12 @@ def test_report_simple_2(test_dir):
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prj = 'light_control'
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ctx = context.TestContext(test_dir, prj, 'report_simple_2', POS_DIR)
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ctx.run()
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ctx.expect_out_file(prj+'-report.txt')
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f_report = os.path.join('report', prj+'-report.txt')
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ctx.expect_out_file(f_report)
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ctx.expect_out_file(prj+'-report_simple.txt')
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ctx.compare_txt(prj+'-report.txt', prj+'-report.txt_2')
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ctx.compare_txt(f_report, prj+'-report.txt_2')
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ctx.compare_txt(prj+'-report_simple.txt')
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ctx.expect_out_file(prj+'-report.pdf')
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ctx.expect_out_file(f_report.replace('.txt', '.pdf'))
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ctx.clean_up(keep_project=True)
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@ -54,5 +54,6 @@ outputs:
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- name: 'report_full'
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comment: "Full design report"
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type: report
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dir: report
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options:
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do_convert: true
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