Adjusted the report tests for KiCad 5.
- Some unknown inconsistency in the API.
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# PCB
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Board size: 59.69x48.26 mm (2.35x1.9 inches)
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- This is the size of the rectangle that contains the board
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- Thickness: 1.6 mm (63 mils)
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- Material: FR4
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- Finish: ENIG
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- Layers: 4
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- Copper thickness: 35 µm
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Solder mask: TOP / BOTTOM
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- Color: Top: Blue / Bottom: Red
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Silk screen: TOP / BOTTOM
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- Color: White
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# Important sizes
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Clearance: 0.15 mm (6 mils)
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Track width: 0.15 mm (6 mils)
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- By design rules: 0.13 mm (5 mils)
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Drill: 0.25 mm (10 mils)
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- Vias: 0.25 mm (10 mils) [Design: 0.2 mm (8 mils)]
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- Pads: 0.6 mm (24 mils)
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Via: 0.51/0.25 mm (20/10 mils)
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- By design rules: 0.46/0.2 mm (18/8 mils)
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- Micro via: no [0.2/0.1 mm (8/4 mils)]
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- Burried/blind via: no
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Outer Annular Ring: 0.25 mm (10 mils)
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- By design rules: 0.25 mm (10 mils)
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Eurocircuits class: 6D
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# General stats
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Components count: (SMD/THT)
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- Top: 61/12 (SMD + THT)
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- Bottom: 0/0 (NONE)
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Defined tracks:
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- 0.15 mm (6 mils)
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- 0.15 mm (6 mils)
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- 0.3 mm (12 mils)
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- 0.64 mm (25 mils)
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Used tracks:
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- 0.15 mm (6 mils) (276) defined: yes
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- 0.3 mm (12 mils) (11) defined: yes
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- 0.64 mm (25 mils) (175) defined: yes
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Defined vias:
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- 0.51/0.25 mm (20/10 mils)
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- 0.51/0.25 mm (20/10 mils)
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- 0.89/0.51 mm (35/20 mils)
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Used vias:
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- 0.51/0.25 mm (20/10 mils) (Count: 23, Aspect: 3.1 A) defined: yes
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- 0.89/0.51 mm (35/20 mils) (Count: 33, Aspect: 1.8 A) defined: yes
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Holes (excluding vias):
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- 0.8 mm (31 mils) (4)
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- 0.85 mm (33 mils) (2)
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- 0.95 mm (37 mils) (3)
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- 1.2 mm (47 mils) (20)
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- 3.2 mm (126 mils) (4)
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# Schematic
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{ width=16.5cm height=11.7cm }
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# PCB Layers
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{ width=16.5cm height=11.7cm }
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{ width=16.5cm height=11.7cm }
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@ -0,0 +1 @@
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../5_1_6/light_control-report.txt_2
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@ -0,0 +1 @@
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light_control-report.txt
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@ -1011,7 +1011,7 @@ def test_report_simple_2(test_dir):
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ctx.run()
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ctx.expect_out_file(prj+'-report.txt')
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ctx.expect_out_file(prj+'-report_simple.txt')
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ctx.compare_txt(prj+'-report.txt')
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ctx.compare_txt(prj+'-report.txt', prj+'-report.txt_2')
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ctx.compare_txt(prj+'-report_simple.txt')
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ctx.expect_out_file(prj+'-report.pdf')
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ctx.clean_up(keep_project=True)
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